1. FPGA structure and programming - Eli Kaminsky 1 FPGA structure and programming

2. FPGA structure and programming - Eli Kaminsky2 Contents: Transistor overview – MOSFET Transistor overview – MOSFET Usages of transistors as switches Usages of transistors as switches Transistors – the building blocks of logical gates Transistors – the building blocks of logical gates The idea of FPGA The idea of FPGA FPGA structure FPGA structure SRAM cells SRAM cells FPGA programming FPGA programming Conclusion Conclusion references references

3. FPGA structure and programming - Eli Kaminsky3 Transistor overview – MOSFET MOSFET: Metal Oxide Semiconductor Field Effect Transistor. It is the most popular type of transistor implementing a simple switch. There are two different types of MOSFETs, NMOS and PMOS. This is a general scheme of an NMOS transistor:

4. FPGA structure and programming - Eli Kaminsky4 A transistor is fabricated by creating areas in the silicon substrate that have either positive or negative excess of electrical charge, type p and type n respectively. The gate is electrically isolated from the rest of the transistor by a layer of silicon dioxide, which is a type of a glass insulator. When Vs = Vg = 0, the source and the drain are isolated by the p type substrate – the transistor is OFF. But what happens if we increase the voltage in the gate terminal with respect to the voltage of the source?

5. FPGA structure and programming - Eli Kaminsky5 The gate terminal is connected to Vdd, resulting in Vgs = 5v. The positive voltage on the gate attracts free electrons that exist in the type n source terminal as well as from other parts of the transistor (electrical field). Electrons form a channel under the layer of glass of type n, connecting the source and the drain. In this case, we say that the transistor is ON. The behavior of PMOS transistors is the same as for NMOS, except that all voltages and currents are reversed. Here we connect source and gate to Vdd for OFF, and gate to zero for ON. We will se an example for that.

6. FPGA structure and programming - Eli Kaminsky6 Usages of transistors as switches An NMOS transistor is turned on when its gate terminal is high, while a PMOS transistor is turned on when its gate is on low. When the NMOS is ON its drain is pulled to the ground, and when the PMOS is on its drain is pulled up to Vdd. We will see and example with the NAND gate, which is a complete logical system.

7. FPGA structure and programming - Eli Kaminsky7 Logical gates NOT gate: When Vx = 0, T2 is OFF and T1 is ON  Vf = Vdd = 5v When Vx = 5v, T2 is ON and T1 is OFF  Vf = 0. There is no current because T1 is OFF. This configuration of PMOS above an NMOS is called CMOS.

8. FPGA structure and programming - Eli Kaminsky8 NAND gate: (any idea on how to make the AND gate?) Logical gates

9. FPGA structure and programming - Eli Kaminsky9 And gate: Simply connect The NOT. Logical gates

10. FPGA structure and programming - Eli Kaminsky10 Logical gates So far we have seen the importance of transistors as switches, and as the building blocks of logical gates. In the mean time, we’ll move on to FPGA. We’ll see more of transistors when we dig deeper into FPGAs, since this component relies heavily on transistors.

11. FPGA structure and programming - Eli Kaminsky11 The idea of FPGA FPGA: Field Programmable Array Logic. FPGA is a programmable logic device that supports implementation of large logic circuits, by providing logic blocks for implementation of the required functions. The FPGA contains three main types of resources: 1. logic blocks 2. I/O blocks 3. interconnection wires and switches

12. FPGA structure and programming - Eli Kaminsky12 The idea of FPGA The interconnection wires have programmable switches that allow the logic blocks to be connected in many ways. We’ll see more of that when we get to programming.

13. FPGA structure and programming - Eli Kaminsky13 The idea of FPGA – logic blocks Each logic block in an FPGA has a number of inputs and ouputs. Here we’ll focus on a small logic block for an example. The most commonly used logic block is LUT – lookup table, which implements a small logic function. Our LUT has two inputs and one output. Since It has two inputs it holds four storage cells to be able to play with the four logical combinations of the inputs – 00 01 10 11. We choose the combination we want, and with three multiplexers we choose the output.

14. FPGA structure and programming - Eli Kaminsky14 The idea of FPGA – logic blocks An LUT example: X1 chooses Mux, 0 for upper and 1 for lower. X2 chooses within the muxes, 0 for upper value and 1 for lower.

15. FPGA structure and programming - Eli Kaminsky15 FPGA structure FPGAs are configured by using ISP method. The storage cells in the LUTs in an FPGA lose their stores contents whenever the chip is turned off. To avoid that, a small memory chip that holds data permanently (PROM) is included on the board that hosts the FPGA, so the storage cells could be loaded back to the FPGA as soon as the chip is on again. Next we’ll see an example of interconnected LUTs in an FPGA.

16. FPGA structure and programming - Eli Kaminsky16 FPGA structure Here we see the three resources, I/Os, logic blocks, and interconnections and switches. Now, imagine that there are two levels of wires, horizontal and vertical. A black X means we did not connect a horizontal wire and a vertical one from different levels. A blue X mean we did.

17. FPGA structure and programming - Eli Kaminsky17 FPGA structure According to the LUT truth table, we get f1 = X1*X2 and f2 = X2’*X3 Lets follow the input and interconnections to see that f = f1 + f2 = x1*x2 + X2’*X3

18. FPGA structure and programming - Eli Kaminsky18 SRAM cells Before we get to FPGA programming we have to get ourselves acquainted with SRAM (static random access memory) cells. SRAM cells are used for the following: 1. They can store a logic value of 0 or 1. 2. They can store a value of an LUT. 3. They configure the interconnection switches of the FPGA. How do we set a value in an SRAM storage cell ?

19. FPGA structure and programming - Eli Kaminsky19 SRAM cells To store data, ‘sel’ is set to to 1 (5v), the NMOS now passes the data from the left hand side to the right hand side of the transistor. After the data stabilizes around the two NOT gates, ‘sel’ is set to 0, and the data remains running forever. Note that the lower NOT is smaller, meaning it has weaker transistors. That is in case we want to set a new data and we want the larger NOT to override the smaller one in case the logical level has to change. Don’t mind the blue line

20. FPGA structure and programming - Eli Kaminsky20 FPGA programming How do we program the switches of the FPGA? SRAMs maybe…? Recall that the vertical wires and the horizontal wires are on different levels. By setting the SRAM cell to the wanted value, we can determine if the cross or not. Cross is 1, don’t cross is 0.

21. FPGA structure and programming - Eli Kaminsky21 FPGA programming Each switch is implemented using NMOS with its gate terminal controlled by an SRAM cell. By controlling all of those SRAM cells, we actually set the system of interconnections.

22. FPGA structure and programming - Eli Kaminsky22 FPGA programming As an example of an FPGA configuration, we’ll be talking about Altera’s Cyclone FPGA.

23. FPGA structure and programming - Eli Kaminsky23 FPGA programming The Cyclone FPGA provides JTAG boundary scan test that complies with IEEE std.1149.1a-1990. The Cyclone FPGA provides JTAG boundary scan test that complies with IEEE std.1149.1a-1990. The Cyclone FPGA uses the JTAG port to monitor the operation of the device. The Cyclone FPGA uses the JTAG port to monitor the operation of the device. Cyclone FPGA supports the following JTAG instructions: Cyclone FPGA supports the following JTAG instructions:

24. FPGA structure and programming - Eli Kaminsky24 FPGA programming

25. FPGA structure and programming - Eli Kaminsky25 FPGA programming The logic, circuitry, and interconnections are configured with CMOS SRAM cells. The logic, circuitry, and interconnections are configured with CMOS SRAM cells. Cyclone devices are configured at system startup with data stored in an Altera configuration device. Cyclone devices are configured at system startup with data stored in an Altera configuration device.

26. FPGA structure and programming - Eli Kaminsky26 Conclusion We saw the bottom – up view of the FPGA, starting from the transistor level. We saw the bottom – up view of the FPGA, starting from the transistor level. We learned what are the main resources of the FPGA. We learned what are the main resources of the FPGA. We learned how the interconnections of the FPGA and its switches are programmed. We learned how the interconnections of the FPGA and its switches are programmed. FPGA is a very flexible logical system to configure. FPGA is a very flexible logical system to configure. FPGA supports JTAG BST technology. FPGA supports JTAG BST technology.

27. FPGA structure and programming - Eli Kaminsky27 references Fundamentals Of Digital Logic With VHDL Design Stephen Brown & Zvonko Vranesic Fundamentals Of Digital Logic With VHDL Design Stephen Brown & Zvonko Vranesic The Arts Of Electronics Paul Horowitz & Winfield Hill The Arts Of Electronics Paul Horowitz & Winfield Hill www.altera.com www.altera.com www.altera.com www.fpga4fun.com www.fpga4fun.com

28. FPGA structure and programming - Eli Kaminsky28 END