1. CS 6020 - Chapter 3 (3A and 10.2.2) – Part 4 of 5
Dr. Clincy
Professor of CS
Dr. Clincy
Lecture
Slide 1 1

2. Half Adder - Combinational Circuits
Combinational logic circuits give us many useful devices.
One of the simplest is the half adder, which finds the sum of two bits.
We can gain some insight as to the construction of a half adder by looking at its truth table, shown at the right.
Dr. Clincy
Lecture

3. Full Adder - Combinational Circuits
We can change our half adder into to a full adder by including gates for processing the carry bit.
The truth table for a full adder is shown at the right.
Dr. Clincy
Lecture

4. Adders - Combinational Circuits
Just as we combined half adders to make a full adder, full adders can be connected in series.
The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder.
Today’s systems employ more efficient adders.
Dr. Clincy
Lecture

5. Decoder - Combinational Circuits
Among other things, they are useful in selecting a memory location according to a binary value placed on the address lines of a memory bus.
This is what a 2-to-4 decoder looks like on the inside.
If x = 0 and y = 1, which output line is enabled?
Output - Decoded message
Input - Encoded message
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Lecture

6. Decoder – another example
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Lecture

7. Multiplexer - Combinational Circuits
A multiplexer does just the opposite of a decoder.
It selects a single output from several inputs.
This is what a 4-to-1 multiplexer looks like on the inside.
Depending the “select input” combination, 1 of 4 data inputs is chosen for output
If S0 = 1 and S1 = 0, which input is transferred to the output?
Dr. Clincy
Lecture

8. Multiplexer - Combinational Circuits
Can also use multiplexers to implement logic functions
Given this truth table, group X1,X2 being 00, 01, 10 and 11 – notice what happens with X3
3-input truth table can be done with a 4-input mux
4-input truth table can be done with a 8-input mux
5-input truth table can be done with a 16-input mux
Etc..
Also explain how the Mux is used to implement data comm’s FDM and TDM
Dr. Clincy
Lecture

9. 10.2.2 - Programmable Logic Devices (PLD)
All possible combinations of inputs ANDed  
•••
All possible combinations of ANDed inputs ORed  
Re-explain Sums of Products and relationship to PLDs
Dr. Clincy
Lecture

10. 10.2.2 - Programmable Logic Array (PLA)
Ability to program a PLD, is called a PLA
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Lecture

11. 10.2.2 - Programmable Array Logic (PAL)
For a PLA, both the AND array and OR array are programmable
For a PAL, the AND array is programmable and the OR array is fixed
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Lecture

12. 10.2.2 - Complex Programmable Logic Devices (CPLDs)
CPLDs are comprised of 2 or more PALs
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Lecture

13. 10.2.2 - Field Programmable Gate Arrays (FPGAs)
PAL chips are somewhat limited in size due to the fact they have output pins for each sum-of-product circuit
FPGA overcome this size limitation by using a general interconnection.
General interconnection
PAL
Dr. Clincy
Lecture

14. CS 3510 - Chapter 3 (3A and 10.2.2) – Part 5 of 5
Dr. Clincy
Professor of CS
Dr. Clincy
Lecture
Slide 14 14

15. Sequential Circuits Vs Combinational Circuits
Sequential Logic
Current State or output of the device is affected by the previous states
Circuit
Flip Flops
New Input
Previous State or Output
Current State or Output
Combinatorial or Combinational Logic
Circuit
New Input
Current State or Output
Current State or output of the device is only affected by the current inputs
Dr. Clincy
Lecture

16. Clock - Sequential Circuits
State changes are controlled by clocks (clock ticks).
Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage – edge triggered.
Level-triggered circuits change state when the clock voltage reaches its highest or lowest level.
Dr. Clincy
Lecture

17. Flip Flops - Sequential Circuits
New Input
Previous State or Output
Current State or Output
Notice how the output feeds the input
Think of: Given R=0 and Qa=0, what can this be ?
S and R stand for set and reset respectively
constructed from a pair of cross-coupled NOR gates
the stored bit is present on the output marked Qa
If S and R inputs are both low, maintains the Qa and Qb in constant state,
If S (Set) is pulsed high while R is held low, then the Qa output is forced high,and stays high even after S returns low;
if R (Reset) is pulsed high while S is held low, then the Qa output is forced low, and stays low even after R returns low.
Dr. Clincy
Lecture

18. Gated SR Latch or Flip Flop
The time at which the latch is SET or RESET is controlled by a CLOCK input
Called Gated SR Latch
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Lecture

19. Gated D Latch Inputs S and R are derived from a single input D
Clock pulse controls when the output is triggered
Samples the D input at the time the clock is HIGH and stores that info until the next clock pulse
During the time the clock is high, the input changed, causing the output to change – this is the problem
Dr. Clincy
Lecture

20. Potential Problem
Thus far, the assumption has been the inputs S and R (or D) not changing while CLK is HIGH
What would happen if S, R and/or D changed ? The output would change immediately
This could be a problem
To fix this (next ppt)
During the time the clock is high, the input changed, causing the output to change – this is the problem
Dr. Clincy
Lecture

21. Two Flip Flop Use To Fix Clock Issue
FF1
FF2 Q Q D D Q m D Q s Q
Clock
Clk Q
Clk Q Q
Use 2 D flip flops – the FF2 clock is set to zero – therefore, if there was a change in FF1 input, D, it wouldn’t effect the FF2 Q value – FF2 holds the value
(a) Circuit
Clock D Q m Q = Q s
Clock’s negative edge causes change
(b) Timing diagram
If D changes while FF1 CLK is HIGH, Qm changes immediately - Qs stays the same because FF2 CLK=0
Once the CLK goes LOW, FF2 reacts because its CLK=1 – so it thens reflects D D Q
The arrow only symbolizes “positive edge” clock - the arrow with the NOT symbolizes “negative edge” clock Q
(c) Graphical symbol
Dr. Clincy
Lecture