ASIC to FPGA Conversion Flow

Conversion Feasibility Flow Chart Design Rules Checking Feasibility Report RTL CodeQuick Conversion ASIC Netlist Fault coverage Testability report Design Rules Report Special Functions Identification Check Die size Check Bond Die / Package Pin-out when applicable ATPG Timing Specification STA

Conversion flow Synthesis Design compiler (Synopsys) Testability Insertion DFT Advisor (Mentor)- Scan BIST Architect (Mentor)- BIST BSD Architect (Mentor) – JTAG (only on used pads) Design Rule Checks Star (in-house) Formal Proof Formality (Synopsys) Nano Route (Cadence) Routing Customer test benches or VCD results Delay Tuning no Logic Simulations Modelsim (Mentor) Placement Silicon Ensemble (Cadence) F.E. Clock Tree Synthesis CTGEN (Cadence) RTL code Behavioral code Timing specification Atmel gate level netlist Post-layout netlist Tester rules check Sign off DRC/LVS TAPE OUT Timing constraints STA Primetime (Synopsys) Simulation Comparison SIRAS (in-house) Simulations yes SDF +Verilog / VHDL net list +ASIC Lib Atmel activity or data Customer activity or data Joint Atmel customer activity