1. Digital System Design Verilog ® HDL Introduction to Synthesis: Concepts and Flow Maziar Goudarzi

2. Objectives Learn – What is synthesis – Understand and appreciate differences between simulation and synthesis – Various synthesis tools – Get ready for the course laboratory and learn its limitations 2010DSD2

3. Logic Synthesis? Why? Assembly coding vs. C/Java programming Gate-level modeling vs. behavioral modeling 2010DSD3

4. Logic Design Course Standard products – Adders 2010DSD4

5. Traditional Logic Design Flow 2010DSD5

6. Logic Synthesis Flow 2010DSD6

7. Logic Synthesis Process of generating detailed logic gates from higher-level description – RTL (Register Transfer Level) / Logic Synthesis – Behavioral Synthesis (High Level Synthesis) Decide number of registers and their interconnects in addition to RTL synthesis 2010DSD7

8. Verilog Lower Abstraction Levels Gate Level Models – All synthesizable Dataflow Models – Most expressions synthesizable – Exceptions: *, /, %, ===, !== General rule – Delays are all ignored 2010DSD8

9. Behavioral Level General rules – All delays ignored – initial blocks not synthesizable – always statements Sensitivity list decides what is synthesized Further details: later in this semester, after ASIC and FPGA internal structures are taught 2010DSD9

10. Famous Synthesis Tools 2010DSD10 CompanyFamous Synthesis Tool (or design environment) Mentor GraphicsLeonardo Spectrum SynopsysDesign Compiler, Synplify CadenceEncounter RTL Compiler, BuildGates Altera (FPGA company)Quartus Xilinx (FPGA company)ISE...The list continues…