1. Logic Synthesis Tutorial
Pusan National University

2. Introduction A new way for logic design
HDL(Hardware Description Language)-based design method
This is what we are studying in this course
First, hierarchical RTL structure and corresponding behavior are thought, and described in HDL by designers
Then, all Boolean logic equations are generated automatically by logic synthesis
Corresponding schematic are also generated automatically by logic synthesis
Much less error-prone, and tedious 2

3. Introduction History of Logic Synthesis
Pioneered by some researchers at IBM and UC Berkeley in 1980’s
Commercialized by Synopsys, the biggest EDA company
Revolutionized the way of logic design
From error-prone manual logic design to error-free automatic logic design 3

4. Introduction Typical Flow of Front-end Design Specification
Architecture Design
RTL design
Functional verification
(e.g. RTL simulation)
Logic synthesis
Gate-level verification
(e.g. gate-level simulation)
To back-end design 4

5. Logic Synthesis Typical Flow Logic synthesis =
Translation + Optimization
Design constraints: speed, power consumption, area, etc
Technology mapping builds an optimized gate-level net-list from technology-dependent cells provided in a technology library
Translation
Technology-independent(TI) optimization
Technology mapping
TI-optimized
(gate-level) net-list
Optimized
Technology
library
RTL design
Design constraints 5

6. Logic Synthesis Example: Serial_adder DUV data_in sum_out SUM REGq b c r ck
reset
clock 6

7. Logic Synthesis Example: Serial_adder(RTL_bahavior) SUM DUV data_in
sum_out
REG
(posedge ck or posedge r)
begin
if ( r == 1 )
q <= 0 ;
else
q <= d ;
end
(a or b)
{c, s} = a + b; q d c b r ck
reset
clock 7

8. Logic Synthesis Example: Serial_adder(Gate-Level_Structure) SUM DUV
- after translation and TI-optimization -
SUM
DUV
data_in a s
sum_out
REG D Q
rst ck q d c b r ck
reset
clock 8

9. Logic Synthesis Example: Serial_adder(Gate-Level_Structure)
- Technology mapping -
Technology Library
INVETER1 cell
INVERTER2 cell
BUFFER1 cell
BUFFER2 cell
NAND2 cell
NAND3 cell
NAND4 cell
NOR2 cell
NOR3 cell
NOR4 cell
AO cell
AOI cell ..
16. 1-bit_HA cell
17. 1-bit_FA cell
25. DFF1_arst1 cell
26. DFF1 cell
DUV
REG
SUM a b s c d q r ck
data_in
sum_out
Cell#16_
1-bit_HA
Cell#25_
DFF1_arst1
reset
clock 9

10. Assignment Logic Synthesis Lab.
Complete your RTL design, write a test bench, and perform RTL simulation
With your example RTL design and Xilinx ISE, perform the entire logic synthesis process to obtain a technology dependent gate-level netlist
At each step in the logic synthesis process with Xilinx ISE, take a screen shot and identify to where it belongs in the typical flow of logic synthesis
You should obtain a gate-level Verilog structural code as the final result, and make a PPT file for a possible presentation including the RTL simulation result 10