1. Speaker: Tsung-Yi Wu FPGA Design Flow (Part 2) : Simulation

2. Documents –http://www.engr.newpaltz.edu/~bai/CSE45 208/ModelSim%20tutorial.pdfhttp://www.engr.newpaltz.edu/~bai/CSE45 208/ModelSim%20tutorial.pdf –http://www.ece.utexas.edu/projects/ee360 m/spring2005/lab_resources/modelsim_tut orial.dochttp://www.ece.utexas.edu/projects/ee360 m/spring2005/lab_resources/modelsim_tut orial.doc –ModelSim  Help  PDF Document

3. Design Process

4. Why Do You Do Simulation? Functional Verification Timing Verification Sign-off RTL Simulation Verification: Design Behave as Required? (Timing/Function) Register-Transfer-Level Logic-Level (Gates) Transistor-Level (Electrical) Synthesis Map Specification to Implementation

5. Why Do You Do Simulation? Functional Verification –Multi-Level Simulation RTL GL Netlist Layout Synthesis Design Implementation SIMULATORSIMULATOR Translate Map Place&Route Translate Map Place&Route

6. Logic Simulation Flow Simulator (Verilog/VHDL) Testbench Netlist Simulation Models SDF SDF extraction Pass/Fail

7. Verilog Software Simulators Mentor ModelSim Silos III Verilog Simulator Synopsys VCS Cadence –Verilog-XL: Interpreter –NC-Sim: Compiler NC-Verilog NC-VHDL Co-Simulation

8. ModelSim Tutorial Starting ModelSim –Start  Programs  ModelSim XE II  ModelSim

9. ModelSim Tutorial Create Project –File  New  Project –Keep Default Library Name

10. ModelSim Tutorial Create Project –After hitting OK, an Add items to the Project dialog pops out –We can add already existing files to the project

11. ModelSim Tutorial Compiling –Select Compile  Compile All

12. ModelSim Tutorial Simulaion –Click on the Library tab of the main window and then click on the (+) sign next to the work library. You should see the name of the module of the code that we have just compiled one. Library Tab

13. ModelSim Tutorial Simulaion –Double-click on the module to load the file –Now select view  All Windows

14. ModelSim Tutorial Simulaion –Locate the signals window and select the signals that you want to monitor for simulation purposes.

15. ModelSim Tutorial Simulaion –Select Simulate  Run  Run -All

16. ModelSim Tutorial Wave Window

17. ModelSim Tutorial Wave Window

18. ModelSim Tutorial Printing the Wave Window –Printing from the wave window is simple as you only need to select: File  Print

19. Invoking ModelSim from ISE Open the Project Navigator by Double- clicking on the ISE Icon or Going to Start  Programs  Xilinx ISE 6  Project Navigator

20. Invoking ModelSim from ISE Add exisiting sources by selecting Project menu  Add Source... Select “ your test-bench ” and click Open. In Choose Source Type Window, Select Verilog Test Fixture File

21. Invoking ModelSim from ISE Test-bench Example: tb_myled.v `timescale 1ns/1ps module tb_led; reg reset,clk; wire[5:0] q; proc u1 (reset,clk,q); initial begin reset=1; clk=0; #8 reset=0; #400; $finish; end always #10 clk=~clk; endmodule

22. Invoking ModelSim from ISE Click your Test- bench in “ Sources in Project ” Area –The simulation models will be shown in “ Process for Source ” area Click

23. Invoking ModelSim from ISE Double-Click Simulate Behavioral Model –ModelSim will be invoked Double-Click Simulate Post-Place & Route Verilog Model –ModelSim will be invoked A *.tdo Is Created for ModelSim to Execute