1. 9 th Sept, 2009 1 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Low Power Implementation of ARM1176JZF-S by Manish Kulkarni

2. 2 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Statement  Input  RTL of ARM1176JZF-S  Implementation process in 65nm CMOS (TSMC)  Power Intent  Library Information (to be used)  Output  Enabling RTL for Low Power design  This includes enabling clock gating  Writing Unified Power Format (UPF) from given power intent  Low Power implementation of ARM1176JZF-S for 45nm CMOS (Samsung)

3. 3 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Outline  Basic implementation Flow  Synthesis  Basic Input Requirements  Decision on Power Intent and Creation of UPF  Understanding Intent and creating Power Intent Diagram  Describing this power intent in UPF  Floor Planning  Placement Optimization  Clock Tree Synthesis (CTS)  Route Optimization  LVS and DRC  Static Timing Analysis (Primetime)  Power Analysis (Primetime PX)  Formal Verification  Remaining work

4. 4 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Basic Flow RTL (Verified) & Design Specs Tool: VCS Synthesis Tool: Design Compiler Floor-planning Tool : ICC Placement Tool : ICC Clock Tree Synthesis (CTS) Tool : ICC Routing Tool : ICC Sign off Includes LVS, DRC Tools: Hercules / Calibre Sign Off : Timing Analysis Tool : Prime Time Sign Off: Power Analysis Tool: PrimeTime PX Sign Off: Formal Verification Tool: Formality GDS II

5. 5 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Basic Requirements Synthesis RTL (Verified) Libraries.lib file Technology specific Design Constraints TLUPLUS Technology file.tf file Tech specific information Unified Power Format (UPF) Specifies power intent of design Tech.tcl script

6. 6 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Decision on Power Intent and UPF creation What is Power Intent ? How many separate power domains do you have? Are these running on different voltages? Are these static or dynamically varied during operation? Do you plan to shutdown any blocks? Do you plan to retain the state of your design during shutdown? In what sequence are the power domains turned on / off? Answers to these questions decide Power Intent of a design

7. 7 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Power Intent Domains dynamically varied during operation? Yes, with the help of an external power controller Running at different voltages ? Yes, 3 different voltages How many Separate Power Domains ? VCORE – Contains most combinational logic and some FF VSOC – contains control logic and maintains communication between VCORE and VRAM VRAM – contains all the RAMs Power Mode VDDCOREVDDRAMVDDSOC High Voltage1.21 v Med Voltage1.14 v 1.21 v Low Voltage0.99 v 1.21 v DormantOFF (0 v)1.21 v

8. 8 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL

9. 9 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Power Intent Diagram VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCOREVDDSOCVDDRAM VSS

10. 10 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Power Intent Diagram VSS VDDSOC CPUCLAMP VSS VDDRAM RAMCLAMP VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCOREVDDSOCVDDRAM VSS

11. 11 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Power Intent Diagram VSS VDDSOC VDDRAM VSS VDDSOC VDDCORE VDDSOC CPUCLAMP VSS VDDRAM RAMCLAMP VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCORE VDDSOCVDDRAM VSS LS VDDRAM VSS VDDCORE

12. 12 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Power Intent Diagram VDDCORE 1.21 V 1.14 V 0.99 V OFF VDDRAM 1.21 V 1.14 V 0.99 V 1.21 V VDDSOC 1.21 V VSS VDDSOC VDDRAM VSS VDDSOC VDDCORE VDDSOC CPUCLAMP VSS VDDRAM RAMCLAMP VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCORE VDDSOCVDDRAM VSS VDDRAM VSS VDDCORE LS

13. 13 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Lets see how the Power Intent Diagram is converted to UPF UPF Power Intent Diagram Writing UPF from Power Intent Diagram

14. 14 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Interpreting Diagram VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCOREVDDSOCVDDRAM VSS create_supply_net create_power_domain create_supply_port

15. 15 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL VSS VDDSOC CPUCLAMP VSS VDDRAM RAMCLAMP VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCOREVDDSOCVDDRAM VSS set_isolation set_isolation_control Interpreting Diagram

16. 16 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL VSS VDDSOC VDDRAM VSS VDDSOC VDDCORE VDDSOC CPUCLAMP VSS VDDRAM RAMCLAMP VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCORE VDDSOCVDDRAM VSS LS VDDRAM VSS VDDCORE set_level_shifter - rule low_to_high set_level_shifter - rule high_to_low Interpreting Diagram

17. 17 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL VDDCORE 1.21 V 1.14 V 0.99 V OFF VDDRAM 1.21 V 1.14 V 0.99 V 1.21 V VDDSOC 1.21 V VSS VDDSOC VDDRAM VSS VDDSOC VDDCORE VDDSOC CPUCLAMP VSS VDDRAM RAMCLAMP VCORE VRAM DEFAULT_VA VDDCOREVDDSOCVDDRAM VDDCORE VDDSOCVDDRAM VSS VDDRAM VSS VDDCORE LS create_pst PST -supplies {VDDCORE VDDRAM VDDSOC} add_pst_state PM_highV -pst PST -state {High High High } add_pst_state PM_medV -pst PST -state {Med Med High } add_pst_state PM_lowV -pst PST -state {Low Low High } add_pst_state VCORE_dormant -pst PST -state {OFF High High } ` Interpreting Diagram

18. 18 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Floorplanning Height Width Spacing from die boundary Initialized core area VRAM VCORE Remaining area treated as DEFAULT_VA(VSOC) VSOC placed between VRAM & VCORE Voltage areas created Placement done in order to reduce total area in VRAM domain Power pins were kept parallel to horizontal power straps Memory Macro placement Around Memory macros and on chip boundary To avoid placement of SC and fillers Placement Blockages are created Fill Ties are added in all VAs

19. 19 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Floorplanning (Cont..) All the logical Power and Ground connections are done separately in each domain Logical Power & Ground (PG) net connection Rings are created around each domain Straps are created over the domains in mesh structure and connected to rings Power Rings & Straps Placement is performed with congestion and timing driven attributes Placement is legalized Filler cells are inserted Placement Pre-routing of SC is done in which power rails are created to connect PG nets Level shifter cells are fixed after pre-routing Pre-routing PG connections verified Filler cells are removed Verify PG

20. 20 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Placement Optimization  The cells in the design are placed in the layout to meet the given timing, area and power constraints  It is an iterative process Violations:  High Fan-out Nets Violations  Constraints reports after synthesis reported 2 high-fan-out nets  CPUCLAMP ( fanout : 1684)  RAMCLAMP ( fanout : 48)  These caused many max_trasition violations  These nets were fixed by  compile_clock_tree –high_fanout_net CPUCLAMP  compile_clock_tree –high_fanout_net RAMCLAMP

21. 21 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL CTS and ROUTE  Clock Tree Synthesis (CTS) :  routes the clock throughout the design  Inserts buffers in the tree so as to meet max. fan-out and max. transition constraints  The cells placed during place optimizations are not modified  Routing  All the interconnection signals are routed  Buffers may be inserted in order to meet timing constraints  Constraints on the metal layers to be used are specified  Iterative process which takes the longest time in the flow

22. 22 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL LVS and DRC  Layout Versus Schematic (LVS)  It is verified weather the layout obtained is same as the schematic specified  The connectivity of the ports and signals is verified as per the schematic  Design Rule check (DRC)  Foundry specifies manufacturing specific design rules  Spacing between 2 metal tracks in same layer etc  Designer has to verify if these rules are being followed properly  Tools like Hercules (Synopsys) and Calibre (Mentor Graphics) can be used  IC Compiler also contains inbuilt tools to check LVS and DRC

23. 23 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Static Timing Analysis  Analysis Performed using Primetime  Post Layout verilog netlist is loaded  Extracted Parasitic are loaded  Timing analysis is performed for only one power state (High voltage) Violations:  Setup and Hold violations were found  Transition violations were found  These violations were fixed by adding buffers in high fan-out nets which are causing these violations  It can also be fixed by increasing the drive strength of cells

24. 24 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Power Analysis  Power Analysis is performed using Primetime PX  Probabilistic logic activity was used for power measurement and the probability was set to 0.25  Analysis was done only for first power state i.e. the high voltage mode Power GroupInternal (W) Switching (W) Leakage (W) Total (Row) (W) % IO pad00000.00 % memory2.033e-035.632e-041.933e-042.789e-0344.30% clock_network2.318e-041.105e-052.745e-045.174e-04 8.22% register6.903e-055.583e-063.601e-044.347e-04 6.90% combinational2.148e-041.777e-035.001e-042.492e-0339.58% sequential4.312e-052.980e-061.690e-056.299e-051.00% Total (Column)2.591e-032.360e-031.345e-036.296e-03 41.16%37.48%21.36%100.00%

25. 25 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Formal Verification  Tool used is Formality (Synopsys)  proves or disproves functional equivalence of two designs  In this case, functionality is verified between the pre-layout gate level netlist (or verified(golden) RTL) and post-layout gate level netlist  Uses static techniques which do not require vector inputs  Uses existing Synopsys Design Compiler technology libraries

26. 26 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Remaining Work Power StateVoltagesPowerFrequency VCOREVRAMVSOC State_High1.21 v 6.296 mW250 MHz State_Med1.14 v 1.21 v?? State_Low0.99 v 1.21 v?? Dormant0 v1.21 v ?? The characterization was done for only High Power state Similar characterization can be done for the other Power states

27. 27 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL Questions

28. 28 9 th Sept, 2009 VLSI Design & Test seminar series, Fall 2009, Auburn University, Auburn, AL THANK YOU !!!