6/5/2016 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Fault Simulation

Fault Simulation Classical Fault Simulation Modern Fault Simulation for Combinational Circuits Modern Fault Simulation for Synchronous Sequential Circuits Parallel and Distributed Fault Simulation Fault Grading --- Approximate Fault Simulation Hardware Approaches to Fault Simulation

1. To evaluate the quality of a test set -- usually in terms of fault coverage 2. To incorporate into ATPG for test generation -- due to its lower complexity 3. To construct fault dictionary -- for post-test diagnosis 4. To analyze the operation of a circuit in the presence of faults -- for reliability analysis Why Fault Simulation?

Conceptual Fault Simulation Logic simulation on both good (fault-free) and faulty circuits Fault-free Circuit Faulty Circuit #1 (A/0) Faulty Circuit #2 (B/1) Faulty Circuit #F (D/0) Primary Inputs (PIs) Primary Outputs (POs) Patterns (Sequences) (Vectors) Response Comparison Detected? AB C D

Verified design netlist Verification input stimuli Fault simulatorTest vectors Modeled fault list Test generator Test compactor Fault coverage ? Remove tested faults Delete vectors Add vectors Low Adequate Stop Fault Simulation

Fault simulation Selection of target faults Select target fault done Generate test for target Fault simulate Discard detected faults No more faults Generate initial T done Evaluate T Sufficient fault coverage? Modify T N Y To evaluate (grade) a test T use fault simulation

Classical Fault Simulation Common Characteristics: In general, no restriction on the circuit types. Developed before VLSI era. Serial Fault Simulation trivial single-fault single-pattern Parallel Fault Simulation Deductive Fault Simulation Concurrent Fault Simulation

Complexity of Fault Simulation Complexity = P * F *G~ O(G 3 ) with single s-a faults The complexity is higher than logic simulation, O(G 2 ), but is much lower than test pattern generation. In reality, the complexity is much lower due to fault colapsing and advanced techniques. #Gate (G) #Pattern (P) #Fault (F)

Serial fault simulation fault specification (includes fault collapsing) fault insertion fault effect generation & propagation fault detection & discarding In parallel fault simulation, a number of faulty circuits are simulated and signal values are represented by vectors

Classical Parallel Fault Simulation Taking advantage of inherent parallel operation of computer words to simulate faulty circuits in parallel with fault-free circuit the number of faults, that can be processed in parallel is limited by the word length. Straightforward and memory efficient Some weaknesses: A value change, of a single fault or fault-free circuit leads to the computation of the entire word. The fault-free logic simulation is repeated for the number of passes.

Example of Parallel Fault Simulation — Bit-space: J/0 B/1 F/0 FF where FF = Fault-free x x x A B C DE F G HJ Consider three faults: B/1, F/0, and J/

Parallel Fault Simulation Applied test pattern: abcde=10010

Parallel Fault Simulation ffa/0b/1c d/0e/1f/0f/1g/0g/1h/0h/1i/0i/1u/0u/1 a= b= c d= f=ab g=(f+c)’ h=cd e= i=e+h u=g+i

Deductive fault simulation Instead of keeping all signal values for all faulty circuits in parallel as in parallel simulation, only a list of faults which causes different responses on a given line is kept F faults signal line i L i = {4, 7} parallel deductive

Deductive Fault Simulation (b) x=1 y=0 z=0 x=1 y=1 x=1 y=0 x=1 y=0 L x  L y L y  L x L x  L y L x  (L y  L z ) (a) g=1 i=0 u=1 h=0 e=0 i=0 f=0 c=0 g=1 f=0 a = 1 b=0 d=1 c=0 h=0 G1 G3 G4 G2 G5 L b  L a  f/1 L g =L f  L c  g/0 L u =(L g  L i  (u/0) L i =L h  L e  i/1 L f =( (L c  L d  h/1 L h =

Rules for deductive simulation jI If C= then L={L}{Z sa(ci)} zj   else L=({L}- {L}){Z sa(ci)} jC j jI-C j    I - input c - controlling values i – inversion value and for the primary inputs set Therefore for AND,OR,NAND,NOR there is no 0,1,0 or 1 respectively on any input and append the output list list with Z/0, Z/1, Z/1, Z/0 respectively So for AND,OR,NAND,NOR when there is 0,1,0 or 1 on their inputs append output list with Z/1, Z/0, Z/0, Z/1 respectively

Deductive fault simulation Besides faults which can propagate through the gate, we add the following output faults c i |c| = 0 |c| > 0 fault fault equivalence dominance AND 0 0 Z0 Z1 I0  Z0 I1 < O1 OR 1 0 Z1 Z0I1  Z1I0 < O0 NAND 0 1Z1 Z0 I0  Z1 I1 < O0 NOR 1 1 Z0 Z1 I1  Z0 I0 < O1

xy AND Lx  Ly  Z/1 (Lx - Ly)  Z/1(Ly  Lx)  Z/1 Lx  Ly  Z/0 OR Lx  Ly  Z/1 (Ly - Lx)  Z/0(Lx - Ly)  Z/0 Lx  Ly  Z/0 NAND Lx  Ly  Z/0 (Lx - Ly)  Z/0(Ly - Lx)  Z/0 Lx  Ly  Z/1 NOR Lx  Ly  Z/0 (Ly - Lx)  Z/1(Lx - Ly)  Z/1 Lx  Ly  Z/1 Deductive fault simulation For two-input gates

Deductive Simulation LEVEL 0LEVEL 1 LEVEL 2LEVEL3 LEVEL4 Node FF PRIMARY INPUTS PRIMARY OUT a1a/0 b0b/1 c0c/1 d1d/0 e0e/1 f (Lb  La)  f/1 = b/1, f/1 g Lf  Lc  g/0 =b/1, f1, c/1, g/0 h (Lc  Ld)  h/1 = c/1,h/1 i Lh  Le  i/1 =c/1,e/1, i/1, h/1 u Lg  Li  u/0 = b/1, f1, g/0, u/0 So Lu = (Lg – Li)  u/0 = ((b/1, f/1, c/1, g/0) -(c/1)) + u/0= b/1, f/1, g/0, u/0, as indicated in the last column g=1 i=0 u=1 h=0 e=0 i=0 f=0 c=0 g=1 f=0 a = 1 b=0 d=1 c=0 h=0 G1 G3 G4 G2 G5 L b  L a  f/1 L g =L f  L c  g/0 L u =(L g  L i  (u/0) L i =L h  L e  i/1 L f =( (L c  L d  h/ 1 L h =

Example of Deductive Simulation x x x A B C D E F G H J Consider 3 faults: B/1, F/0, and J/0 and test t1={1,0,1} L B = {B/1}, L F = {F/0}, L A = Ø L C =L D = {B/1}

x x x A B C D E F G H J Consider 3 faults: B/1, F/0, and J/0 L B = {B/1}, L F = {F/0}, L C =L D = {B/1}, L G = {B/1}, L E = {B/1} Example of Deductive Simulation

x x x A B C D E 1 F G H J Consider 3 faults: B/1, F/0, and J/0 L B = {B/1}, L F = {F/0}, L C =L D = {B/1}, L G = {B/1}, L E = {B/1}, L H = {B/1, F/0} Example of Deductive Simulation

x x x A B C D E 1 F G 0 H 1 J Consider 3 faults: B/1, F/0, and J/0 L B = {B/1}, L F = {F/0}, L C =L D = {B/1}, L G = {B/1}, L E = {B/1}, L H = {B/1,F/0}, L J = {F/0,J/0} Example of Deductive Simulation

x x x A B C D E 1 F G 0 H 1 J L B = {B/1}, L F = {F/0}, L C =L D = {B/1}, L G = Ø, different set for t2={0,0,1} L E = {B/1}, L H = {B/1,F/0}, L J = {B/1,F/0,J/0} When A changes from 1 to 0 Example of Deductive Simulation

Deductive fault simulation Example : After fault collapsing, the set of faults we simulate is { a0, a1, b1, c0, c1, d1, e0, g0, h0, h1} Perform deductive fault simulation using test vector t1={00110} 1 k abcdeabcde f 0 ghgh j 0 i 1 1m1m

Deductive fault simulation Assume the first applied test vector is t1={00110} L a = {a 1 }, L b = {b 1 }, L c = {c 0 }, L d = , L e = , L f = L a L b = , L g = L c  {g 0 }={c 0,g 0 }, L h = L c  {h 0 } = {c 0, h 0 }, L j = L g - L f = {c 0, g 0 }, L i = L d  L h = {c 0, h 0 }, L k = L i - L e = {c 0, h 0 }, L m = L k - L j = {h 0 } 1 k abcdeabcde f0f ghgh j 0 i 1 1m1m Fault list { a0, a1, b1, c0, c1, d1, e0, g0, h0, h1} x=1 y=0 L y  L x x=0 y=0 z=0 y=1 L x  L y L x  (L y  L z ) L x  L y y=0 L y  L x 

Example Using test vector t2={1,1,0,1,0} Fault list after fault collapsing { a0, a1, b1, c0, c1, d1, e0, g0, h0, h1} 0 k abcdeabcde f1f ghgh 0j0i0j0i 0m0m Start with L a = {a 0 }, L b = , L c = {c 1 }, L d = , L e = 

Deductive Fault list L a = {a 0 }, L b = , L c = {c 1 } L d = , L e =  L f = L a  L b = {a 0 } L g = L c = {c 1 } L h = L c  {h 1 } = {c 1,, h 1 } L i = L h - L d = {c 1,, h 1 } L j = L f - L g = {a 0 } L k = L i  L g = {c 1,, h 1 } L m = L j  L k = {a 0,c 1, h 1 } Faults detected in this step of deductive simulation

Concurrent Fault Simulation Each gate retains a list of fault copies and each of them stores the status of a fault different from fault- free values. Simulation is similar to the regular fault simulation except that only the difference w.r.t. fault-free circuit is retained. Very versatile in circuit types and gate delays Although theoretically all faults in a circuit can be processed in one pass, memory explosion restricts the fault number in each pass.

Fault List of AND Gate A B D A/1 B/1 D/1 faults

a b c d e f g a0a0 b0b0 c0c0 e0e0 a0a0 b0b0 b0b0 c0c0 e0e0 d0d0 d0d0 g0g0 f1f1 f1f1 Concurrent Fault Simulation

Fault List Propagation A B D C E A B D C E A/1: 10_0C/1: 01_1 B/1: 01_0D/1: 10_1 D/1: 00_1E/1: 00_1 *A/0: 00_0*B/1: 10_1 E/1: 00_1 *B/1: 11_1 C/1: 01_1 *D/1: 10_1 D/1: 10_1 * faults Inputs and output

Example of Concurrent Simulation x x x A B C D E F G HJ Consider 3 faults: B/1, F/0, and J/0 L G = {10_0, B/1:11_1} L E = {0_1, B/1:1_0} Inputs_output Fault: Faulty inputs_output signal

x x x A B C D E 1 F G HJ Consider 3 faults: B/1, F/0, and J/0 L G = {10_0, B/1:11_1} L E = {0_1, B/1:1_0} L H = {11_1, B/1:01_0, F/0:10_0} Example of Concurrent Simulation

x x x A B C D E 1 F G 0 H 1J Consider 3 faults: B/1, F/0, and J/0 L G = {10_0, B/1:11_1} L E = {0_1, B/1:1_0} L H = {11_1, B/1:01_0, F/0:10_0} L J = {01_1, B/1:10_1, F/0:00_0, J/0:01_0} Example of Concurrent Simulation

x x x A B C D E 1 F G 0 H 1J When A changes from 1 to 0 L G = {00_0, B/1:01_0} L E = {0_1, B/1:1_0} L H = {11_1, B/1:01_0, F/0:10_0} L J = {01_1, B/1:00_0, F/0:00_0, J/0:01_0} Example of Concurrent Simulation

Concurrent Simulation G1abf G2 cfgG3cdhG4ehiG5gIu a/0000b/1010c/ b/ c1/1100d/0000e/1101c/1011 f/1101 f /1010h/ e/1111 g/0000i/1001 f /1000 g/0000 h/1111 i/1111 u/0100 Gates and their inputs Detectable faults in bold Possible faults Faulty responses

Fault Simulation Unused output B faults not detected Tied to ground Exercise