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Lecture 13 Sequential Circuit ATPG Time-Frame Expansion

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1 Lecture 13 Sequential Circuit ATPG Time-Frame Expansion
Problem of sequential circuit ATPG Time-frame expansion Nine-valued logic ATPG implementation and drivability Complexity of ATPG Cycle-free and cyclic circuits Asynchronous circuits Summary Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

2 Sequential Circuits A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

3 Example: A Serial Adder
An Bn 1 1 s-a-0 X D 1 1 D X Cn Cn+1 X 1 1 Combinational logic Sn X FF Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

4 Time-Frame Expansion Time-frame -1 Time-frame 0 An-1 Bn-1 An Bn Cn-1
s-a-0 D X s-a-0 D D 1 1 Cn-1 1 D X Cn 1 D 1 Cn+1 X 1 Combinational logic Combinational logic 1 Sn-1 Sn X D FF Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

5 Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Vector -n+1 Vector -1 Vector 0 Fault Unknown or given Init. state State variables Next state Time- frame -n+1 Time- frame -1 Time- frame Comb. block PO -n+1 PO -1 PO 0 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

6 8 8 X Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

7 1 1 1 Step 1 1 D D D X s-a-1 Copyright 2001, Agrawal & Bushnell
D D X D s-a-1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

8 Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 13

9 1 1 1 Step 2 1 D Step 2 1 D 1 D D D D 1 D D D D X s-a-1
1 1 Step 2 1 D Step 2 1 D 1 D D D D 1 D D X D D s-a-1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

10 1 1 1 1 D 1 D 1 Step 3 1 D D 1 D D 1 D D D D D D D D 1 1 D D D D D D
1 1 D 1 D 1 Step 3 1 D D 1 D D 1 D D D D D D D D 1 1 D D X D D D s-a-1 D T(x/1)=1 1 1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

11 Example for Logic Systems
FF1 B D’ A FF2 s-a-1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

12 Five-Valued Logic (Roth) 0,1, D, D, X
A s-a-1 s-a-1 D D X X X FF1 FF1 X D D FF2 FF2 B X B X Time-frame -1 Time-frame 0 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

13 Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A X s-a-1 s-a-1 X X 0/X 0/X FF1 FF1 0/1 X/1 X 0/1 X/1 FF2 FF2 X X B X B 0/1 Time-frame -1 Time-frame 0 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

14 Implementation of ATPG
Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

15 Drivability Example (11, 16) (10, 15) (22, 17) (10, 16) d(0/1) = 8
s-a-1 d(0/1) = 4 d(1/0) = d(0/1) = d(1/0) = 20 8 8 (5, 9) (4, 4) (17, 11) d(0/1) = 9 d(1/0) = (CC0, CC1) = (6, 4) (6, 10) d(0/1) = 120 d(1/0) = 27 8 FF d(0/1) = 109 d(1/0) = 8 CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

16 max = Number of distinct vectors with 9-valued elements = 9Nff
Complexity of ATPG Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit – Contains feedback among flip-flops: May need 9Nff time-frames, where Nff is the number of flip-flops. Asynchronous circuit – Higher complexity! Smax Time- Frame max-1 Time- Frame max-2 S3 Time- Frame -2 S2 Time- Frame -1 S1 Time- Frame S0 max = Number of distinct vectors with 9-valued elements = 9Nff Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

17 Generation of Self-Initializing Test Sequence:
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

18 Example 6.19: Z s-a-0 Test sequence=? I-State= unknown
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

19 Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 13

20 1 Time frame 0 x 1 x x ? x x 1 x 1 x x 1 ? 1 2 x x x D I X
x x ? x x 1 x 1 I x x 1 ? 1 2 x x x D X Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

21 1 Time frame 1 1 1 x x x ? 1 x x 1 x 1 1 1 1 1 ? 1 2 x x x 1 x D I
1 1 x x x ? 1 x x 1 x 1 I 1 1 q+1q2+ =(0,1) 1 1 ? 1 2 x x x 1 x D X Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

22 1 Time frame 2 1 1 1 x x x ? 1 x x 1 x 1 I 1 1 1 1 q+1q2+ =(0,1) T = (00 1) 1 1 1 ? 1 1 2 x x D x 1 x 1 1 D X D Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

23 Cycle-Free Circuits Characterized by absence of cycles among flip-flops and a sequential depth, dseq. dseq is the maximum number of flip-flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

24 All faults are testable. See Example 8.6.
Cycle-Free Example Circuit D A B X Z C F2 2 E F3 F1 3 Level = 1 F1 F2 F3 Level = 1 2 3 s - graph dseq = 3 All faults are testable. See Example 8.6. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

25 Example 8.6. F1 F2 F3 x T = ( x0,11,11,1x) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

26 X Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

27 Cyclic Circuit Example
Modulo-3 counter Z CNT F2 F1 s - graph F1 F2 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

28 Modulo-3 Counter Cyclic structure – Sequential depth is undefined.
Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. Circuit can only be functionally tested by multiple observations. Functional tests, when simulated, give no fault coverage. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

29 Adding Initializing Hardware
Initializable modulo-3 counter Z CNT F2 F1 s-a-0 s-a-1 CLR s-a-1 s-a-1 Untestable fault Potentially detectable fault s - graph F1 F2 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

30 Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 13

31 Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth
Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 18 529 Cycle-free 4 1242 1239 3 99.8 100.0 313 10 s1238 14 18 508 Cycle-free 4 1355 1283 72 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -- 1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -- 1506 1379 2 30 97 91.6 93.4 28 559 19183 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

32 Asynchronous Circuit An asynchronous circuit contains unclocked memory often realized by combinational feedback. Almost impossible to build, let alone test, a large asynchronous circuit. Clock generators, signal synchronizers, flip-flops are typical asynchronous circuits. Many large synchronous systems contain small portions of localized asynchronous circuitry. Sequential circuit ATPG should be able to generate tests for circuits with limited asynchronous parts, even if it does not detect faults in those parts. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

33 Asynchronous Model C CK Synchronous PIs Combinational Feedback Paths:
Feedback set Feedback-free Combinational Logic C PPI PPO CK Synchronous POs System Clock, CK Clocked Flip-flops Fast model Clock, FMCK Feedback delays Modeling circuit is Shown in orange. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

34 Asynchronous feedback
Time-Frame Expansion Vector k PI Feedback set Feedback set C CK C FMCK C FMCK C FMCK PPI PPO Asynchronous feedback stabilization PO Time-frame -k+1 Time-frame -k-1 Time-frame k Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

35 Asynchronous Example s-a-0 1 1 s-a-0 s-a-0 1 X 1 1 s-a-0 1 s-a-0 s-a-0
1 1 1 s-a-0 s-a-0 1 X 1 1 s-a-0 s-a-0 s-a-0 s-a-1 s-a-0 Vectors Outputs Gentest results: Faults: total 23, detected 15, untestable 8 (shown in red), potentially detectable none Vectors: 4 Sparc 2 CPU time: test generation 33ms, fault simulation 16ms Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

36 Summary Combinational ATPG algorithms are extended:
Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time Cycle-free circuits: Require at most dseq time-frames Always initializable Cyclic circuits: May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free (Chapter 14) Asynchronous circuits: High complexity Low coverage and unreliable tests Simulation-based methods are more useful (Section 8.3) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13

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