1. Exclusive Test and its Application to Fault Diagnosis Vishwani D. Agrawal Dong Hyun Baik Yong C. Kim Kewal K. Saluja Kewal K. Saluja

2. Agrawal, Baik, Kim and Saluja: VLSI Design 20032 Overview ► Problem Statement ► Introduction  Background on Diagnosis  Definitions for Diagnosis ► Main Idea  Exclusive Test  Example of Exclusive Test  Exclusive Test Generation  Properties of Exclusive Test ► Diagnosis Method ► Results ► Conclusion

3. Agrawal, Baik, Kim and Saluja: VLSI Design 20033 Problem Statement ► Obtain high resolution diagnostic test using a single-fault ATPG.

4. Agrawal, Baik, Kim and Saluja: VLSI Design 20034 Introduction: Background on Diagnosis ► Single-fault dictionary approaches  Simulation based: Chang et al. Fault Diagnosis of Digital Systems, NY, Wiley-Interscience, 1970 Fault Diagnosis of Digital Systems, NY, Wiley-Interscience, 1970  Most common method for diagnosis ► Diagnostic test pattern generation: Specialized ATPGs  Implication based: Gruning et al. DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational circuits - ICCAD, 1991 DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational circuits - ICCAD, 1991  Multiple-pass strategy: Savir et al. - Testing for, and Distinguishing between Failures - FTCS, 1982

5. Agrawal, Baik, Kim and Saluja: VLSI Design 20035  Diagnostic dictionary Introduction: Definitions for Diagnosis ► Consider CUT on the right  All 10 faults are detected by 5 test vectors: T 1 = 001, T 2 = 010, T 3 = 011, T 4 = 101, T 5 = 111 T1T2T3T4T5T1T2T3T4T5T1T2T3T4T5T1T2T3T4T5 a1a1a1a1 1 0 1 0 0 b1b1b1b1 0 0 0 1 0 c0c0c0c0 0 0 1 0 1 c1c1c1c1 0 1 0 1 0 d1d1d1d1 0 0 0 1 0 f1f1f1f1 0 0 1 0 0 g0g0g0g0 0 0 0 0 1 h0h0h0h0 0 1 0 0 0 i0i0i0i0 0 1 0 0 1 i1i1i1i1 1 0 1 1 0 s-a-1 Add T 6 = 000 T6T6T6T60 1 0 0 0 0 0 0 0 1 ● DR = 10/9=1.11 ► 10 Faults, but only 9 syndromes: b 1 and d 1 cannot be distingushied b 1 and d 1 cannot be distingushied ● DR = 10/10=1.00 ► 10 syndromes: b 1 and d 1 are now distinguished b 1 and d 1 are now distinguished test syndrome for fault g 0 Diagnostic Resolution (DR). Diagnostic Resolution (DR).  DR = No. of faults (classes) No. of syndromes No. of syndromes  A measure of quality of diagnosis

6. Agrawal, Baik, Kim and Saluja: VLSI Design 20036 Main Idea ► Exclusive test  An Input vector that detects only one fault from a pair of targeted faults at a primary output  C 0 : A fault free circuit  C 1 : CUT with fault f 1  C 2 : CUT with fault f 2

7.  Diagnostic dictionary Example of Exclusive Test ► Application  Generate an additional vector to improve diagnostic resolution: distinguish a pair of faults, b 1 and d 1. distinguish a pair of faults, b 1 and d 1. ► Example T1T2T3T4T5T1T2T3T4T5T1T2T3T4T5T1T2T3T4T5 a1a1a1a1 1 0 1 0 0 b1b1b1b1 0 0 0 1 0 c0c0c0c0 0 0 1 0 1 c1c1c1c1 0 1 0 1 0 d1d1d1d1 0 0 0 1 0 f1f1f1f1 0 0 1 0 0 g0g0g0g0 0 0 0 0 1 h0h0h0h0 0 1 0 0 0 i0i0i0i0 0 1 0 0 1 i1i1i1i1 1 0 1 1 0 s-a-1 T 6 = 000 T6T6T6T60 1 0 0 0 0 0 0 0 1

8. Agrawal, Baik, Kim and Saluja: VLSI Design 20038 Exclusive Test Generation Kim, Agrawal and Saluja - “Multiple Faults: Modeling, Simulation and test” VLD 2002 Exclusive test for (b 1,d 1 ), T 6 = 000 0 0 0 D b1b1 d1d1

9. Agrawal, Baik, Kim and Saluja: VLSI Design 20039 Properties of Exclusive Test ► If there exists an exclusive test two faults then they can be distinguished from each other by using that test. ► If no exclusive test exists then the faults cannot be distinguished; two faults form an equivalent fault set.

10. Agrawal, Baik, Kim and Saluja: VLSI Design 200310 Diagnosis Method Start with fault detection tests Make dictionary and isolate undiagnosed fault sets Generate an exclusive test for an undiagnosed fault pair Is DR satisfactory? Test exists? Done Yes No Yes Append the test ATPG aborted Form an equiv. Fault set No

11. Agrawal, Baik, Kim and Saluja: VLSI Design 200311 Results: Model Results: Model ► For illustration, an XOR-tree is added to the output of the circuit under test to make it a single output circuit.  We use * to denote a modified circuit with a single output XOR-tree at its outputs. ► General multiple-PO case is discussed later.

12. Agrawal, Baik, Kim and Saluja: VLSI Design 200312 Test Generation − ISCAS85 Circuits Circuit names c432* c880* c1908* c3540* # of fault detection tests82104176239 # of equiv. collapsed faults52494218793428 # of redundant faults45490 # of aborted faults022781 # of detected faults52093518483257 Fault coverage (%)99.2499.2698.3595.01 Fault efficiency (%)10099.7998.5697.57

13. Circuit names c432* c880* c1908* c3540* # of faults52093518483257 # of syndromes42678914502706 # of diagnosed faults35468611212351 Diagnostic resolution ( DR)1.221.191.271.20 Max. faults per syndrome56812 # of fault detection vectors82104176239 # of syndromes50687015792844 # of diagnosed faults49280813312559 Diagnostic resolution (DR)1.031.071.171.14 Max. faults per syndrome2388 Total test vectors126152262328 # of exclusive tests added44488689 # of equivalent pairs0001 # of aborted pairs1479321662 Diagnostic Results − ISCAS85 Circuits

14. Agrawal, Baik, Kim and Saluja: VLSI Design 200314 Test Generation − c432 Detection tests c432* c432 # of fault detection tests82 # of equiv. collapsed faults524 # of redundant faults444 # of aborted faults000 # of detected faults520 Fault coverage (%)99.24 Fault efficiency (%)100

15. Diagnostic Results − c432 Circuit names c432* c432 # of faults520 # of syndromes428495500 # of diagnosed faults354471479 Diagnostic resolution (DR)1.221.051.04 Max. faults per syndrome554 # of fault sets506507 # of syndromes506507 # of diagnosed faults492494 Diagnostic resolution (DR)1.00 Max. faults per syndrome111 Total test vectors131 123 # of exclusive tests491341 # of equivalent pairs1413 # of aborted pairs000 C432: Simulated using tests derived with c432*, then targeted only undiagnosed faults

16. Agrawal, Baik, Kim and Saluja: VLSI Design 200316 Conclusion ► Definition of an exclusive test and an ATPG method are introduced. ► A comprehensive exclusive test based diagnostic method is presented where a conventional single fault ATPG can be used. ► Results for ISAS85 benchmark circuits are presented.

18. Agrawal, Baik, Kim and Saluja: VLSI Design 200318 Supplement 1: Multiple Fault Model Equivalent Single Stuck-at fault ► Kim, Agrawal and Saluja -  “Multiple Faults: Modeling, Simulation and test” - VLSI Design,2002  Convert multiple fault test generation problem into single fault test generation problem. s-a-1 Multiple (4) stuck-at fault s-a-1 s-a-0

19. Agrawal, Baik, Kim and Saluja: VLSI Design 200319 Supplement 2: Test Generation − ISCAS85 Circuits Circuit names c17* c432* c499* c880* c1355* c1908* c2670* c3540* # of detection tests 68258104 176236239 # of equiv. faults 225247589421574187927473428 # of redundant faults 0405048490 # of aborted faults 00322 2788481 # of detected faults 225207269351542184817793257 Fault coverage (%) 10099.2495.7899.2697.9798.3564.7695.01 Fault efficiency (%) 100 95.7899.7997.9798.5666.897.57

20. Circuit names c17* c432* c499* c880* c1355* c1908* c2670* c3540* # of faults225207269351542184817793257 # of syndromes14426691789873145012852706 # of diagnosed faults935466168636011219722351 DR1.571.221.051.191.771.271.381.2 Max. faults per syndrome4546118 12 Diagnosis with detection and exclusive tests # of faults225207269351542184817793256 # of syndromes22506710870902157913852844 # of diagnosed faults22492694808366133110972559 DR11.031.021.071.711.171.281.14 Max. faults per syndrome122338118 Total test vectors1112672152129262293328 # of exclusive tests544144825865789 # of equivalent pairs00000001 # of aborted pairs0141679744321630662 Supplement 3: Diagnostic Results − ISCAS85 Circuits