1. Oct. 5, 2001Agrawal, Kim and Saluja1 Partial Scan Design With Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ 07974 va@agere.com Yong C. Kim and Kewal K. Saluja University of Wisconsin, Dept. of ECE Madison, WI 53706 kimy@ece.wisc.edu and saluja@engr.wisc.edu October 5, 2001

2. Oct. 5, 2001 Agrawal, Kim and Saluja 2 Problem Statement Partial scan design has less DFT overhead, but is less desirable than full-scan because it requires sequential ATPG. Partial scan design has less DFT overhead, but is less desirable than full-scan because it requires sequential ATPG. Problem: To devise a combinational ATPG method for general acyclic (cycle-free) circuits; cyclic structures can be made acyclic by partial scan. Problem: To devise a combinational ATPG method for general acyclic (cycle-free) circuits; cyclic structures can be made acyclic by partial scan. FF1 FF2 A cyclic circuitAcyclic partial scan circuit

3. Oct. 5, 2001 Agrawal, Kim and Saluja 3 Overview 1. Combinational ATPG for general acyclic circuits  Background: Previous results and relevant ideas  Balanced model for combinational ATPG  Single-fault model for multiple-faults  Results 2. Special subclasses of acyclic circuits  Background: Definitions and ATPG properties  Examples  Results 3. Conclusion

4. Oct. 5, 2001 Agrawal, Kim and Saluja 4 Previous Work: ATPG Models for Acyclic Sequential Circuits  Iterative array model (Putzolu and Roth, IEEETC, 1971)  Duplicated fan-in logic model (Miczo, 1986)  Duplicated logic model (Kunzmann and Wunderlich, JETTA, 1990)  Balanced structure (Gupta, et al., IEEETC, 1990)  Pseudo-combinational model (Min and Rogers, JETTA, 1992)

5. Oct. 5, 2001 Agrawal, Kim and Saluja 5 Two Relevant Results  Theorem (Bushnell and Agrawal, 2000): A test for a testable non-flip-flop fault in a cycle-free (acyclic) circuit can always be found with at most d seq +1 time-frames.  Balanced circuit (Gupta, et al., IEEETC, 1990): An acyclic circuit is called balanced if all paths between any pair of nodes have the same sequential depth. A combinational ATPG procedure guarantees a test for any testable fault in a balanced circuit.

6. Oct. 5, 2001 Agrawal, Kim and Saluja 6 An Example FF Unbalanced nodes s-a-0 FF replaced by buffer s-a-0 a b a1a1 b1b1 a0a0 b0b0 Balanced model 0 X 1 1 Combinational vector 0 1/0 1 Test sequence: 11, 0X d seq = 1 s-a-0 Multiple fault Single fault

7. Oct. 5, 2001 Agrawal, Kim and Saluja 7 A Combinational ATPG System for General Acyclic Sequential Circuits Generate a balanced model, map faults Generate a test vector for a target fault using combinational ATPG Simulate the comb. model to drop detected faults No More faults to be detected? Yes Obtain a test sequence from comb. vectors

8. Oct. 5, 2001 Agrawal, Kim and Saluja 8 A Single-Fault Model for a Multiple-Fault Y. C. Kim, V. D. Agrawal, and K. K. Saluja, “Multiple Faults: Modeling, Simulation and Test,” 15 th International Conf. on VLSI Design, January 2002. Multiple stuck-at fault: lines a and b stuck-at 1 and line c stuck-at 0. A B C b c a s-a-1 s-a-0 An equivalent single stuck-at fault: output of AND gate stuck-at 1 s-a-1 A B C b c a

9. Oct. 5, 2001 Agrawal, Kim and Saluja 9 Proof of Correctness Fault equivalence: Faulty output functions Fault equivalence: Faulty output functions A mf = 1 B mf = 1 B mf = 1 C mf = 0 C mf = 0 A B C b c a s-a-1 s-a-0 Fault equivalence: Faulty output functions Fault equivalence: Faulty output functions A sf = a + 1 = 1 B sf = b + 1 = 1 B sf = b + 1 = 1 C sf = c · 0 = 0 C sf = c · 0 = 0 s-a-1 A B C b c a Circuit equivalence: Fault-free output functions Circuit equivalence: Fault-free output functions A = a + a ·b ·!c = a B = b + a ·b ·!c = b B = b + a ·b ·!c = b C = c ·!(a ·b ·!c) = c · (!a + !b + c) =c ·(!a + !b) + c = c C = c ·!(a ·b ·!c) = c · (!a + !b + c) =c ·(!a + !b) + c = c s-a-1 A B C b c a

10. Oct. 5, 2001 Agrawal, Kim and Saluja 10 Acyclic Circuit Comb. ATPG Example An example Acyclic circuit with 4 FFs 6 2 5 4 3 X 7 FF2 1 A B C FF1 FF3 FF4 Y D Q D s-a-1 6 2 5 4 3 X: W(X) = 2 7 B C FF1 FF3 FF4 Y D Q D FF2 1 A D Q s-a-1 FF2 1 D Q s-a-1 0 0 1 1 Step 2: Balance with respect to PO X. 6 2 5 4 3 X: W(X) = 2 7 B2B2 C2C2 FF1 FF3 FF4 Y D Q D1D1 FF2 1 D Q s-a-1 FF2 1 D Q s-a-1 0 0 1 1 A0A0 B0B0 A1A1 B1B1 Step 2: Apply DAS to PI A and B. 6 2 5 4 3 X 7 B2B2 C2C2 FF1 FF3 FF4 Y: W(Y) = 2 D Q D1D1 FF2 1 D Q s-a-1 FF2 1 D Q s-a-1 0 0 1 1 A0A0 B0B0 A1A1 B1B1 Step 2: Balance with respect to PO Y. 6 2 5 4 3 X 7 B2B2 C2C2 FF1 FF3 FF4 Y D1D1 FF2 1 s-a-1 FF2 1 s-a-1 0 0 1 1 A0A0 B0B0 A1A1 B1B1 Step 3: Replace FFs with buffers. 6 2 5 4 3 X 7 B2B2 C2C2 FF1 FF3 FF4 Y D1D1 FF2 s-a-1 FF2 0 1 1 0 A0A0 B0B0 1 1 A1A1 B1B1 Example of multiple fault modeling. Step 1: Levelization, assign weights to POs. 6 2 5 4 3 X: W(X)=2 7 FF2 1 A B C FF1 FF3 FF4 Y: W(Y)=2 D Q D s-a-1

11. Oct. 5, 2001 Agrawal, Kim and Saluja 11 ISCAS ’89 Benchmark Circuit: S5378 Circuit statistics ) Circuit statistics ) Number of gates: 2,781 Number of gates: 2,781 Number of FFs: 179 Number of FFs: 179 Number of faults: 4,603 Number of faults: 4,603 ATPG run on Sun Ultra Sparc 10 workstation *TetraMax (comb. ATPG) + Gentest (seq. ATPG)

12. Oct. 5, 2001 Agrawal, Kim and Saluja 12 Acyclic Partial-Scan ISCAS’89 Circuits: Test Generation Results FC: cov. (%), FC: efficiency (%), TGT: CPU s Sun Ultra 10 *Gentest for seq. and TetraMAX for comb. ATPG (Hitec produced equivalent FC, FE and TGT within 10% of Gentest)

13. Oct. 5, 2001 Agrawal, Kim and Saluja 13 Acyclic Partial-Scan ISCAS’89 Circuits: Circuit Statistics

14. Oct. 5, 2001 Agrawal, Kim and Saluja 14 Acyclic Background: Subclasses of Acyclic Circuits Internally balanced (IB) circuit: Becomes balanced by splitting of PI fanouts (Fujiwara, et al., IEEETC, 2000) Internally balanced (IB) circuit: Becomes balanced by splitting of PI fanouts (Fujiwara, et al., IEEETC, 2000) Strongly balanced (SB) circuit : A balanced circuit having the same depth from a PO to all reachable PIs (Balakrishnan and Chakradhar, VLSI Design’96) Strongly balanced (SB) circuit : A balanced circuit having the same depth from a PO to all reachable PIs (Balakrishnan and Chakradhar, VLSI Design’96) Sequential IB SB B Combinational Balanced (B) circuit : All paths between any pair of nodes (PIs, POs, gates or FFs) have the same sequential depth (Gupta, et al., IEEETC, 1990) Balanced (B) circuit : All paths between any pair of nodes (PIs, POs, gates or FFs) have the same sequential depth (Gupta, et al., IEEETC, 1990)

15. Oct. 5, 2001 Agrawal, Kim and Saluja 15 Examples of Acyclic Subclasses An example Acyclic circuit with 4 FFs 6 2 5 4 3 X 7 FF2 1 A B C FF1 FF3 FF4 Y D Q D 6 2 5 4 3 X 7 FF2 1 A B C FF1 FF4 Y D Q D FF3out FF3in An Internally Balanced structure, requires 1 scan FF 6 2 5 4 3 X 7 1 A B C Y D FF3out FF3in FF2out FF2in FF1in FF1out FF4out FF4in A Combinational (Full-scan) requires 4 scan FFs A Balanced structure, requires 2 scan FFs 6 2 5 4 3 X 7 1 A B C FF1 FF4 Y D Q D FF3out FF3in FF2out FF2in A Strongly Balanced structure, requires 3 scan FFs 6 2 5 4 3 X 7 1 A B C FF4 Y D Q D FF3out FF3in FF2out FF2in FF1in FF1out

16. Oct. 5, 2001 Agrawal, Kim and Saluja 16 Number of Scan FFs for Acyclic Subclasses IB: Internally balanced, B: Balanced, SB: Strongly balanced

17. Oct. 5, 2001 Agrawal, Kim and Saluja 17 Comb. ATPG Coverages for Acyclic Subclasses ATPG: TetraMAX Gentest and Hitec produced similar coverages

18. Oct. 5, 2001 Agrawal, Kim and Saluja 18 ATPG CPU Seconds for Acyclic Subclasses ATPG: TetraMAX (on Sun Ultra workstation) Gentest and Hitec show similar proportions

19. Oct. 5, 2001 Agrawal, Kim and Saluja 19 Test Lengths for Acyclic Subclasses VL: Number of combinational ATPG vectors CC: Sequential test clock cycles (x1,000) for scan sequences

20. Oct. 5, 2001 Agrawal, Kim and Saluja 20 Conclusion  Using a balanced circuit model and combinational ATPG, we can generate tests for any acyclic sequential circuit with equal or higher fault coverage and efficiency than obtained by sequential ATPG.  The proposed ATPG procedure provides comparable fault coverage and efficiency with significantly lower DFT (partial-scan) overhead as compared to internally balanced, balanced, strongly balanced and combinational subclasses.  The multiple fault model has new applications to diagnosis, logic optimization, multiply-testable faults, and bridging faults (see VLSI Design’02 paper).

21. Oct. 5, 2001 Agrawal, Kim and Saluja 21 Papers  Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model,” Proc. 14 th Int. Conf. VLSI Design, Jan. 2001, pp. 143- 148.  Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Combinational Test Generation for Various Classes of Acyclic Sequential Circuits,” Proc. Int. Test Conf., Oct. 2001.  Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Multiple- Faults: Modeling, Simulation and Test,” Proc. 15 th Int. Conf. VLSI Design, Jan. 2002.

22. Oct. 5, 2001 Agrawal, Kim and Saluja 22 Thank you