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Veeraraghavan Ramamurthy

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Presentation on theme: "Veeraraghavan Ramamurthy"— Presentation transcript:

1 Veeraraghavan Ramamurthy
Entropy Veeraraghavan Ramamurthy 2/23/2019 ELEC 7250 VLSI Testing Spring'05

2 ELEC 7250 VLSI Testing Spring'05
Simulation Logic Simulator True value simulation. Fault Simulator Simulation in presence of fault. 2/23/2019 ELEC 7250 VLSI Testing Spring'05

3 ELEC 7250 VLSI Testing Spring'05
Algorithm Parse the netlist. Generate random input vectors. Obtain output of each level and propagate it to the primary output. 2/23/2019 ELEC 7250 VLSI Testing Spring'05

4 ELEC 7250 VLSI Testing Spring'05
Compaction Generate a unique output list. Compare the bits output vectors to see the number of bits changed. Based on the percentage set either consider or discard the vector. 2/23/2019 ELEC 7250 VLSI Testing Spring'05

5 ELEC 7250 VLSI Testing Spring'05
Results Input Output Unique O/P Unique I/P Compact set 50% 10% 2/23/2019 ELEC 7250 VLSI Testing Spring'05

6 Fault coverage comparison
Random vectors read vector: 1 det faults 8 coverage read vector: 2 det faults 14 coverage read vector: 3 read vector: 4 read vector: 5 det faults 19 coverage read vector: 6 det faults 20 coverage read vector: 7 read vector: 8 Compact set For 50% read vector: 1 det faults 8 coverage read vector: 2 det faults 16 coverage For 10% det faults 14 coverage read vector: 3 det faults 19 coverage 2/23/2019 ELEC 7250 VLSI Testing Spring'05

7 ELEC 7250 VLSI Testing Spring'05
Inference For a 3 bit input circuit maximum input possible is 8 vectors, which is compacted to 2 vectors if we use 50% as desired percentage and 3 vectors if 10% is used. Total faults in the circuit is 23, random set detected 20 faults, compact set with 50% detected 16 faults and compact set with 10% detected 19 faults. The fault coverage for random input vectors is 86.95% and for the compact set it is 69.56% for 50% & 82.6% for 10% change. 2/23/2019 ELEC 7250 VLSI Testing Spring'05

8 ELEC 7250 VLSI Testing Spring'05
Conclusion Fault coverage of the compact set was found to be less than the coverage of random vector set. Decrease in fault coverage is due to the algorithm used for compaction. 2/23/2019 ELEC 7250 VLSI Testing Spring'05

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