® Additional Spartan-XL Features. ® www.xilinx.com Family Highlights  Spartan (5.0 Volt) family introduced in Jan. 98 —Fabricated on advanced 0.5µ process.

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Presentation transcript:

® Additional Spartan-XL Features

® Family Highlights  Spartan (5.0 Volt) family introduced in Jan. 98 —Fabricated on advanced 0.5µ process technology  SpartanXL (3.3 Volt) family introduced in Nov. 98 —Fabricated on advanced 0.35µ process technology —Power management features —Higher performance over Spartan (5.0 Volt) —Entire family of 5 devices under $7.50  Both families offer: —SRAM technology (re-programmable) —Leverage industry standard XC4000 architecture —Lowest cost FPGA families with memory (SelectRAM) —Extensive core support —Broadest density/package/temperature/speed offering

® Spartan Series Roadmap Spartan $3 95 per 5K gates Price SpartanXL $2 49 per 5K gates Spartan-II up to 100K gates 0.5  3LM Higher Density + More Features Without Compromises Pricing competitive with ASICs High Performance On-chip SelectRAM TM PCI LogiCORE + AllianceCORE 3.3 Volt 5 Volt *Prices are for >100K units, slowest speed, lowest cost package 0.25  5LM Spartan Next Generation up to 200K gates 1.8 Volt 0.18  Higher Speed Lower Power Power Down Mode 0.35  5LM 2.5 Volt

® Spartan/XL Product Matrix CS packages available only in SpartanXL family

® Chip Scale Packages for SpartanXL  XCS10XL and XCS20XL in CS144  XCS30XL and XCS40XL in CS280  0.8 mm pitch solder ball spacing  Higher in I/O count and smaller than any competitive offering in the industry  Reduces board space  Adds 19 more I/Os to the XCS40XL

® XC4000SpartanSpartanXL M0 MODE:M0: Master Serial, Master Serial, Slave Serial Slave Serial M1Don’t ConnectM1: Express M2Don’t Connect Powerdown Mode Pins

® XCS20XL in PQ208 Adds 8 VCCs vs. XCS20  3V XCS20XL adds 8 VCC pins that are not available in the 5V XCS20 —Pads weren’t available on XCS20 die —Extra VCC pins are more important at higher speed and lower VCC —Bonded out to same locations as in XCS30/XL —P18, P33, P71, P86, P121, P140, P173, P192 —Currently NCs on 5V XCS20  Don’t connect these to GND or other signals now that they are VCC!

® Spartan Speed Grades  Spartan speed grades increment from an arbitrary number (“-3”, “-4”) —No correspondence to a physical delay  Former system of using LUT delay no longer applicable at ~1ns  LUT alone does not reflect overall clock speed or routing speed New

® Performance E Spartan, 5V SpartanXL, 3V E-1 E-2 Spartan -4 Spartan SpartanXL-5 SpartanXL-4 PCI Speed Grades  Higher speed grade = higher performance

® DeviceBUFGPBUFGSBUFGLSBUFGE Spartan 4400 SpartanXL 0080 XC4000X 0088 General recommendation: Design with BUFG Software chooses appropriate specific buffer BUFGP/BUFGS will convert to BUFGLS automatically for SpartanXL target Global Clock Buffers

® CLB Latch  CLB flip-flops can be used as latches  LD, etc. components in SpartanXL library  Simplifies use of HDL synthesis  Similar to XC4000X

® Interconnect  Carry only propagates upward —Significantly higher speed –Similar to XC4000X —Standard long line can be used to continue at the bottom of the next column  All other device routing is identical to 5V Spartan family Carry Chain:UpDown Spartan XX SpartanXL X

® 5V Compatibility Can be driven by any 5V device and can drive 5V TTL (default) Any 5 V device SpartanXL FPGA Advanced 0.35  3.3V Core 3.3V I/O 5V 3.3V 5V 3.3V Meets TTL Levels

® Optional 3.3V Clamp for PCI  Programmable global 3.3V clamp for 3V PCI  Sacrifices 5V compatibility  BITGEN option —Default is “5V Tolerant I/Os”

® Output Drive  Programmable 12 mA or 24 mA output drive —Pin-by-pin option —Default is 12 mA —24 mA option supports 5V PCI V/I requirements —Similar to XC4000XLA

® IOB Output Mux  Output 2:1 mux or 2-input LUT in IOB supported in silicon and software —OMUX2, OAND2, etc. in SpartanXL library  Can use BUFGLS to drive one of the inputs for a fast path through the device

® Fast Capture Latch  IOB fast capture latch supported in silicon and software —SpartanXL library includes ILFFX, etc.  Note that there are no “fast” clock buffers —BUFGLS would be used to drive fast capture latch

® KE XCS30XL 6KA 10KA Spartan 6K 10K 2.5V3.3V 5.0V SpartanXL K Factor = 11 Lowest K Factor

® Power Down Pin  /PWRDWN pin activates low-power standby mode —Occupies the M2 pin on the corresponding XC4000E device —Active Low —Timing is asynchronous

®  All inputs (including M0, M1, DONE, CCLK and TDO) except /PWRDWN are disconnected from their sources —The internal nodes are pulled to GND  All pull-up and pull-down resistors on all I/Os (except /PWRDWN) are disabled  The GSR net is active throughout Power Down  The GTS net is active throughout Power Down What Power Down Does

®  Clear the “5 V tolerant I/Os” option  Disable the internal pull-up resistor for /PWRDWN  Avoid contention  Avoid internal oscillators  Run at 3.3V and 25C —Will be specified over operating conditions once characterization is complete To Achieve I CCO =100  A During Power Down...

® Boundary Scan  PowerDown pin taken out of scan chain —BSDL files are different than 5V Spartan  Added IDCODE Instruction —Becomes default instruction  Simplified configuration via boundary scan  Similar to XC4000XLA

® Bitstream  Different format than 5V Spartan bitstream —1 more bit/frame, 1 more frame —Express mode is completely different

® Express Mode  M1 pin enables Express Mode configuration —True parallel configuration –Similar to XC4000XLA —Default pull-up prevents Express mode —Use “BITGEN -g ExpressMode:Enable -g CRC:Disable”

® New Features in SpartanXL Family  Higher speed (-4/-5)  8 flexible global low-skew buffers (BUFGLS)  CLB latches and Input Fast Capture Latch  Output multiplexer or lookup table  3.3V supply for low power with 5V tolerance —3V input clamp for 3V PCI, 24 mA output drive for 5V PCI  Power-down pin  Improved boundary scan  Express parallel configuration mode  Chip Scale packages