1. Academy - High Volume FPGAsPage 1 February 1999 High-Volume FPGAs Xilinx Academy February 1999

2. Academy - High Volume FPGAsPage 2 February 1999 Contents (7:45-9:45) oHigh-Volume FPGA Organization oSpartan Marketing Message oSpartan Architecture oSpartanXL Features oSpartan Software oOther Families oAppLINX and Data Book Status

3. Academy - High Volume FPGAsPage 3 February 1999 XC4000E 1996 XC4000E 1997 High Volume Product Families Performance XC5200 1996 Cost Effective XC5200 1997 Spartan 1Q 1998 SpartanXL 4Q 1998 New: in ‘98 No Compromises! Performance, RAM, Cores, Low Prices

4. Academy - High Volume FPGAsPage 4 February 1999 Product Families: Spartan/XL:ASIC Replacement with RAM Plus … XC2000, XC3000, XC5200 Key Contacts: PrimarySecondary Spartan/XLJay AggarwalSteve Sharp Kurt Wong XC2000/3000/A/L:Ed ChewDaniel Chan XC5200:Kurt WongSteve Sharp Competitive Analysis:Mark MoranAshok Chotai Application Support:Rick MitchellMarc Baker Kim Goldblatt Tactical MarketingFrank CarboneDaniel Chan Denise Gibbons High Volume FPGA Group

5. REFERENCE:

6. Academy - High Volume FPGAsPage 6 February 1999 Spartan Series FPGAs

7. Academy - High Volume FPGAsPage 7 February 1999 No Compromises oHigh Performance —Up to 80 MHz system performance oOn-Chip SelectRAM TM oWide range of IP and CORE solutions —PCI LogiCORE + AllianceCORE oFully integrated software support —Alliance and Foundation Series software oVolume Pricing competitive with ASICs Addresses the key needs of high volume logic users

8. Academy - High Volume FPGAsPage 8 February 1999 Spartan Series Breaks The Mold to Penetrate New Applications oSimultaneous world-wide rollout (Jan 12, 98) oExtensive use of alternative media to reach broad audience —Sales kits, billboards, airport kiosks, ads, disti promos, web pages

9. Academy - High Volume FPGAsPage 9 February 1999 Xilinx Spartan Series FPGAs Xilinx 4000 Heritage Total Cost Management Advanced Process Technology 80 MHz Performance On-chip SelectRAM Software and cores Smallest die size Low packaging cost Low test cost

10. Academy - High Volume FPGAsPage 10 February 1999 Total Cost Management oLeading edge process technology —Smallest die size of any FPGA with on-chip RAM oFocused package offering —Low-power architecture allows use of highest volume plastic packages –PLCC, VQ, TQ, PQ, BGA oStreamlined test flow —Lower cost test hardware —Built-in self test features —Shorter test times oOptimized manufacturing flows

11. Academy - High Volume FPGAsPage 11 February 1999 Spartan Series Opens New Markets and Applications oNo compromises: —Performance —On-chip RAM (SelectRAM) —CORE support —Low cost oNo compromises: —Performance —On-chip RAM (SelectRAM) —CORE support —Low cost oXilinx’s 2nd-generation ASIC alternative oDrive volumes higher —Aggressive pricing oXilinx’s 2nd-generation ASIC alternative oDrive volumes higher —Aggressive pricing oPrice leader for mainstream low- density FPGA market

12. Academy - High Volume FPGAsPage 12 February 1999 FPGA Design Win Focus Select Family Based on Logic Cells Spartan/XL Estimated design size (logic cells) 1500238 20,000 XC4000XLA/XVVirtex S05/XL S10/XL S20/XL S30/XL S40/XL 4013XLA 4020XLA… 4085XLA 40110XV... 40250XV V50 V100 V150 V200 V300 V400 V600 V800 … V1000 28,000

13. Academy - High Volume FPGAsPage 13 February 1999 Existing Design Strategy XC4000E XC4000XL XC5200 Do Nothing Different Do not convert existing designs to Spartan

14. Academy - High Volume FPGAsPage 14 February 1999 Spartan Series Is Here Today oAll Spartan Family devices available —Faster SpartanXL -5 coming soon o-4 devices available now —Enables 33 MHz PCI LogiCORE oCOREs and software available —All Spartan Family devices in Base packages

15. Academy - High Volume FPGAsPage 15 February 1999 Spartan Series Roadmap 1998 19992000 Spartan $3 95 per 5K gates Spartan $3 95 per 5K gates Price SpartanXL $2 95 per 5K gates SpartanXL $2 95 per 5K gates 0.35  5LM SpartanII up to 100K gates SpartanII up to 100K gates 0.5  3LM 2.5 Volt Higher Density + More Features Without Compromises Pricing competitive with ASICs High Performance On-chip SelectRAM TM PCI LogiCORE + AllianceCORE 3.3 Volt 5 Volt *Prices are for 100K units, slowest speed, lowest cost package 0.25  5LM Spartan Next Generation up to 200K gates Spartan Next Generation up to 200K gates 1.8 Volt 0.18  Higher Speed Lower Power Power Down Mode

16. Academy - High Volume FPGAsPage 16 February 1999 Density (System Gates) 199719981999200020012002 15K 40K 100K 100K unit volume price projections 60K New Applications Set Top Box DVD Digital Camera PC Peripherals Consumer Electronics New Applications Set Top Box DVD Digital Camera PC Peripherals Consumer Electronics 25K 60K 200K 100K 10K Gates/$ in 2002! Priced for High-Volume Leadership

17. Academy - High Volume FPGAsPage 17 February 1999 Identifying the Spartan Arena oWhat are typical ASIC densities? oWhat are typical ASIC clock speeds? oWhat packages are most common for ASICs? oWhat cores are popular for ASICs and how often are they used?

18. Academy - High Volume FPGAsPage 18 February 1999 Spartan Arena Covers ASIC Designs Up To 40,000 Gates Dataquest 1997 Gate Array Design Starts by Gate Count The Spartan Arena

19. Academy - High Volume FPGAsPage 19 February 1999 Spartan Arena Covers ASIC Designs Up To 80 MHz Dataquest 1997 ASIC Design Starts by Average Clock Speed The Spartan Arena

20. Academy - High Volume FPGAsPage 20 February 1999 Spartan Arena Covers ASIC Designs from 84-256 Pins Dataquest 1997 ASIC Design Starts by Pin Count The Spartan Arena

21. Academy - High Volume FPGAsPage 21 February 1999 Spartan Arena Addresses Most Popular ASIC Cores Many CORES require RAM (PCI, DSP, USB, etc.) Dataquest 1997 ASIC Designs By Core Usage The Spartan Arena

22. Academy - High Volume FPGAsPage 22 February 1999 Identifying the Spartan Arena of ASIC Designs oUp to 40,000 system gates oUp to 80 MHz system performance o84-256 package pins oRAM and/or COREs used oUp to 200K units/year

23. Academy - High Volume FPGAsPage 23 February 1999 The Battlefield: Gates vs. I/Os ASIC WINS SPARTAN WINS! “The Spartan Arena”

24. Academy - High Volume FPGAsPage 24 February 1999 Leverage Your Strengths: On-chip RAM Expands the Spartan Arena “The Spartan Arena” On-chip RAM

25. Selling SelectRAM Memory Wrong question: Do you need on-chip RAM ? Many users may not know what this means, therefore answer no. Correct qualifying questions: 1. Did you know the Spartan resources can be used as either logic or RAM? 2. Does your design require multiple, small memory functions (<64 words)? For example: Fast FIFOs, LIFOs, accumulators, register stacks, temporary storage registers 3. Do you want to eliminate on / off chip delays to external memory? 4. Do you need 100% burst transfer rate for your PCI interface? 5. Do you need to minimize chip count and maximize system performance? REFERENCE:

26. Academy - High Volume FPGAsPage 26 February 1999 Spartan Series Changes the Battlefield for ASIC Designs oLeverage Spartan Series FPGA price leadership oFocus on high-I/O applications oLeverage on-chip RAM and COREs oLeverage FPGA benefits against ASICs —In-system programming, field upgrades, easy prototyping —No ASIC can deliver these benefits!

27. Academy - High Volume FPGAsPage 27 February 1999 Spartan Series Makes Altera Play By Our Rules Design Requirement? FLEX 10KFLEX 6K Altera On-Chip RAM Performance Gates-only Design Requirement? Xilinx On-Chip RAM Performance Low Cost Altera still using “2 family” compromise strategy Low costHigh cost

28. Academy - High Volume FPGAsPage 28 February 1999 Spartan Series Features Eliminate Competitive FPGAs oGoal: Leverage on-chip RAM and COREs against other FPGAs oTactic: Establish on-chip RAM as an absolute requirement for ASIC-alternative FPGA solutions —Used in 75% of ASIC designs —Used in many FPGA COREs —Spartan Series delivers on-chip RAM at ASIC prices

29. Academy - High Volume FPGAsPage 29 February 1999 Project Aggressive Future Pricing Use Spartan Series Advantages In The Quoting Process oUse “bracketing” in quotes to show options —Quote a multiple device sizes (downward) —Quote prices based on timeframe for orders —Quote different voltage options (Spartan vs. SpartanXL) —Quote volume stepped pricing oVolume price steps strictly enforced

30. Academy - High Volume FPGAsPage 30 February 1999 Call To Action oFind ASIC applications in the Spartan Arena and design-in Spartan Series FPGAs oWin back FLEX 10K 5-volt sockets oKeep FLEX 6K from getting any high- volume design wins

31. Academy - High Volume FPGAsPage 31 February 1999 Spartan Architecture

32. Academy - High Volume FPGAsPage 32 February 1999 Spartan FPGA Architecture oArray of Configurable Logic Blocks (CLBs) oPerimeter Input/Output Blocks (IOBs)

33. Academy - High Volume FPGAsPage 33 February 1999 CLB oTwo Look-Up Tables (LUTs) create any function of four inputs oTwo dedicated flip-flops

34. CLB Flip-Flop oAsynchronous set or reset —Local or global oProgrammable clock polarity oClock enable REFERENCE:

35. Academy - High Volume FPGAsPage 35 February 1999 IOB IK EC

36. Academy - High Volume FPGAsPage 36 February 1999 Single-Port RAM oRegistered write oAsynchronous read

37. Academy - High Volume FPGAsPage 37 February 1999 Dual-Port RAM Added:

38. Logic Gates RAM Size (K bits) 25 20 15 10 XCS30 10000 15000 20000 XCS40 Select the Size No wasted resources Scaleable to needed size Select the Function Can be Single or Dual Port “Mix and match” Select the Location Can be located anywhere on die Adjacent to critical circuits for speed Select the Programming Method Via Bitstream on start-up During design operation SelectRAM Memory Advantages REFERENCE:

39. Academy - High Volume FPGAsPage 39 February 1999 Interconnect oChannel interconnect of varying lengths —“Segmented” interconnect minimizes capacitance —Maximizes speed and minimizes power oSingle/double- length lines and long lines

40. Academy - High Volume FPGAsPage 40 February 1999 Configuration oSingle “Mode” Pin on 5V Spartan —High (default) = Slave Serial –Externally-controlled configuration —Low = Master Serial –FPGA-controlled configuration (from SPROM) oM1 pin on 3V SpartanXL enables parallel Express Mode oMode pin(s) cannot be used as I/O oJTAG configuration supported

41. Academy - High Volume FPGAsPage 41 February 1999 Mode Pins XC4000SpartanSpartanXL M0 Master Serial Master Serial /Slave Serial /Slave Serial M1Don’t Connect/Express M2Don’t Connect /Powerdown

42. Academy - High Volume FPGAsPage 42 February 1999 Pinouts oPQ208 pinout has been optimized —New pinout adds up to 9 I/Os, 8 VCCs —Optimizes noise oOther packages are not pinout- compatible with XC4000E due to MODE pin

43. New Spartan PQ208 Pin-Out oNew pin-out adds —9 I/O pins on the XCS30XL and XCS40XL —8 V CC pins on the XCS20XL, XCS30XL and XCS40XL —The number of GND pins stays the same oNew pin-out NOT compatible with XC4000XL’s oMany corner pins moved (V CC, GND, CLK, etc.) REFERENCE:

44. Academy - High Volume FPGAsPage 44 February 1999 Xilinx Spartan Series 5 Volt ->XCS05XCS10XCS20XCS30XCS40 3.3 Volt ->XCS05XLXCS10XLXCS20XLXCS30XLXCS40XL System Gates 2K-5K3K-10K7K-20K10K-30K13K-40K Logic Cells23846695013681862 Max Logic Gates 3,0005,00010,00013,00020,000 Flip-Flops 360616112015362016 Max RAM bits 3,2006,27212,80018,43225,088 Max Avail. I/O 77112160192205 Performance 80MHz80MHz80MHz80MHz80MHz No Compromises: Performance, RAM, Cores, and Low Price

45. Academy - High Volume FPGAsPage 45 February 1999 Spartan Series Footprint Compatibility oHighest volume ASIC plastic packages oFootprint compatible in common packages 5 VoltXCS05XCS10XCS20XCS30XCS40 3.3 VoltXCS05XLXCS10XLXCS20XLXCS30XLXCS40XL 84 pinPC84PC84 100 pinVQ100VQ100VQ100VQ100 144 pinTQ144TQ144TQ144 208 pinPQ208PQ208PQ208 240 pinPQ240PQ240 256 pinBG256BG256 Underlined = available in Industrial range

46. Academy - High Volume FPGAsPage 46 February 1999 XCS##XL -3PC84C XCS = Spartan XL = 3.3 Volt no XL = 5 Volt ## = System Gates Spartan Naming oLogic cells are the best comparison metric —Will be used in all collateral and comparisons oSpartan part name uses “System Gates ” —Includes both RAM and Logic –Top end of current “gate range” —Matches ASIC industry terminology (+ HardWire) —Consistent with future FPGA families

47. Calculating System Gates oXCS30 and XC4013E have 1368 logic cells —576 CLBs * 2.375 Logic Gate CountSystem Gate Count Logic Gates16,41613,133 (12 gates/LC)(1368 * 12)(80% of 16,416) RAM Gates+ 0 + 17,000 (4 gates/bit) (not included)(20% of 576 * 32 * 4 + available flip-flops) __________________________________________________________ Total Gates~16,000~30,000 REFERENCE:

48. Academy - High Volume FPGAsPage 48 February 1999 Spartan Speed Grades oSpartan speed grades increment from an arbitrary number (“-3”, “-4”) —No correspondence to a physical delay oCurrent XC4000 “-1”/”-09” do not correspond to LUT delay oLUT alone does not reflect overall clock speed or routing speed

49. Academy - High Volume FPGAsPage 49 February 1999 Spartan Speed Grades Performance 5200 4000E Spartan,5V SpartanXL,3V E-1 E-2 Spartan -4 Spartan -3 oHigher Spartan speed grade = higher performance -4 -3 SpartanXL-5 SpartanXL-4

50. Academy - High Volume FPGAsPage 50 February 1999 Spartan -4 Benchmarks oPin-to-Pin I/O speed is fast

51. Academy - High Volume FPGAsPage 51 February 1999 Spartan Differences from XC4000E oNo Asynchronous RAM —No RAM16X1, RAM32X1 – –Only RAM16(32)X1S, RAM16X1D (synchronous) oNo Edge Decoders (wide AND of I/Os) —No DECODEx oNo Wired-AND of BUFTs —No WANDx or WOR2AND oNo Parallel Configuration Modes (only serial) oMode Pins Not Usable as I/O —No MD0, MD1, MD2

52. Academy - High Volume FPGAsPage 52 February 1999 Spartan Cannot Fit an Existing XC4000 Socket oDifferent pinout due to Mode pins —Different PQ208 pinout oDifferent package offering oDifferent functionality oDifferent bitstreams oDifferent timing

53. Academy - High Volume FPGAsPage 53 February 1999 SpartanXL New Features

54. Academy - High Volume FPGAsPage 54 February 1999 Global Clock Buffers DeviceBUFGPBUFGSBUFGLSBUFGE Spartan4400 SpartanXL0080 XC4000X0088 oGeneral recommendation: Design with BUFG —Software chooses appropriate specific buffer —BUFGP/BUFGS will convert to BUFGLS automatically for SpartanXL target

55. Academy - High Volume FPGAsPage 55 February 1999 SpartanXL CLB Latch oCLB flip-flops can be used as latches oLD, etc. components in SpartanXL library oSimplifies use of HDL synthesis oSimilar to XC4000X

56. Academy - High Volume FPGAsPage 56 February 1999 SpartanXL Interconnect oCarry only propagates upward —Significantly higher speed –Similar to XC4000X —Standard long line can be used to continue at the bottom of the next column oDatasheet figure shows upward carry only —Text describes that it is bidirectional in the 5V Spartan family oAll other device routing is identical to 5V Spartan family

57. Carry Chain oThe software will place and route according to the Spartan family oBe careful when using LOC commands Carry Chain:UpDown SpartanXX SpartanXLX REFERENCE:

58. Academy - High Volume FPGAsPage 58 February 1999 SpartanXL 5V Compatibility oCan be driven by any 5V device and can drive 5V TTL (default) Any 5 V device SpartanXL FPGA Advanced 0.35  3.3V Core 3.3V I/O 5V 3.3V 5V 3.3V Meets TTL Levels

59. Academy - High Volume FPGAsPage 59 February 1999 Optional 3.3V Clamp for PCI oProgrammable global 3.3V clamp for 3V PCI oSacrifices 5V compatibility oBITGEN option –Default is “5V Tolerant I/Os”

60. Academy - High Volume FPGAsPage 60 February 1999 SpartanXL Output Drive oProgrammable 12 mA or 24 mA output drive —Pin-by-pin option —Default is 12 mA —24 mA option supports 5V PCI V/I requirements —Similar to XC4000XLA

61. Academy - High Volume FPGAsPage 61 February 1999 Power Down o/PWRDWN pin activates low-power standby mode —Occupies the M2 pin on the corresponding XC4000E device —Active Low —Timing is asynchronous

62. Academy - High Volume FPGAsPage 62 February 1999 What Power Down Does oAll inputs (including M0, M1, DONE, CCLK and TDO) except /PWRDWN are disconnected from their sources —The internal nodes are pulled to GND oAll pull-up and pull-down resistors on all I/Os (except /PWRDWN) are disabled oThe GSR net is active throughout Power Down oThe GTS net is active throughout Power Down

63. Academy - High Volume FPGAsPage 63 February 1999 To Achieve I CCO = 100  A during Power Down... oClear the “5 V tolerant I/Os” option oDisable the internal pull-up resistor for /PWRDWN oAvoid contention oAvoid internal oscillators oCurrently specified as typical —Will be specified over operating conditions once characterization is complete

64. Academy - High Volume FPGAsPage 64 February 1999 SpartanXL Output Mux oOutput 2:1 mux or 2-input LUT supported in silicon and software —OMUX2, OAND2, etc. in SpartanXL library oCan use BUFGLS to drive one of the inputs for a fast path through the device

65. SpartanXL Fast Capture Latch oIOB fast capture latch supported in silicon and software —SpartanXL library includes ILFFX, etc. oNote that there are no “fast” clock buffers —BUFGLS would be used to drive fast capture latch REFERENCE:

66. SpartanXL Boundary Scan o“M2” pin taken out of scan chain —BSDL files are different than 5V Spartan oAdded IDCODE Instruction —Becomes default instruction oSimplified configuration via boundary scan oSimilar to XC4000XLA REFERENCE:

67. Academy - High Volume FPGAsPage 67 February 1999 SpartanXL Bitstream oDifferent format than 5V Spartan bitstream —1 more bit/frame, 1 more frame —Express mode is completely different oMust run BITGEN in M1.5 to program a SpartanXL device

68. Academy - High Volume FPGAsPage 68 February 1999 SpartanXL Express Mode oM1 pin enables Express Mode configuration —True parallel configuration –Similar to XC4000XLA —Default pull-up prevents Express mode —Use “BITGEN -g ExpressMode:Enable -g CRC:Disable” in M1.5.21 or later (hidden)

69. Academy - High Volume FPGAsPage 69 February 1999 XCS20XL PQ208 Adds 8 VCCs oXCS30 PQ208 added 8 VCCs vs. XC4000 oXCS20 PQ208 had no additional VCC pads oXCS20XL adds 8 VCC pads —More important at higher speed/lower VCC —Bonded out to same locations as in XCS30/XL —P18, P33, P71, P86, P121, P140, P173, P192 —Currently NCs on 5V XCS20 oMake sure customers don’t connect these to GND or other signals now that they are VCC!

70. Academy - High Volume FPGAsPage 70 February 1999 Software Support for Spartan Rev. Software Capability 1.5 Spartan LibrariesX SpartanXL LibrariesX Spartan ImplementationX Spartan Speed FileX SpartanXL ImplementationX SpartanXL Speed FileFTP

71. Academy - High Volume FPGAsPage 71 February 1999 SpartanXL Speed Files oImproved speeds from -3/-4 to -4/-5 —Slower SpartanXL comparable to fast 5V Spartan —Speed for free! oAdvance speed files in 1.5i oPreliminary (production) speed files in 1.5i Service Pack —No changes to numbers

72. Academy - High Volume FPGAsPage 72 February 1999 CORE Solutions *Prices are for 100K units, plastic package XCS30XL Percentage of Effective Core Function Price Device Used Function Cost UART$6.9517%$1.30 16-bit RISC Processor$6.9536%$2.60 16-bit, 16-tap$6.9527%$2.00 Symmetrical FIR Filter Reed-Solomon Encoder$6.956%$0.50 LogiCORE PCI32 Spartan$8.2545%$3.80 (in PQ208)

73. Academy - High Volume FPGAsPage 73 February 1999 Costs Less Than Standard ICs Standard Chip External PLD 7K Gates 7K Gates Logic Component cost 100K units Standard Chip PCI Master I/F XCS20XL-4 TQ144* Solution <$7 PCI Master I/F * Supported devices: XCS20XL XCS30XL XCS40XL Power by $5 $20 $10 $15

74. Other Customer Files oIBIS models available now —www.xilinx.com/techdocs/htm_index/sw_ibis.htm oPreliminary BSDL models available now —www.xilinx.com/techdocs/htm_index/sw_bsdl.htm REFERENCE:

75. Academy - High Volume FPGAsPage 75 February 1999 Spartan vs. FLEX

76. Academy - High Volume FPGAsPage 76 February 1999 What is FLEX 6000? oFLEX 6000 = Lower Price Replacement for 8K —Based upon 1994 XC5200 technology —Positioned as “first” Gate Array replacement FPGA 6000 Advantages Improved FLEX 8K routing 50% less expensive than 10K Equivalent performance to 8K Faster than 5200 6000 Disadvantages Limited devices available today No RAM, no I/O Flip-Flops Limited footprint compatibility Slower than Spartan/XC4000 Non-Segmented Interconnect Limited software support

77. Academy - High Volume FPGAsPage 77 February 1999 Spartan Advanced 0.5  Process Chip Transistor gates 0.5m - allows 5 V supply All other features 0.35  - small size - low capacitance - performance - low power Combines 5 V operation with 0.35  benefits

78. Academy - High Volume FPGAsPage 78 February 1999 Relative Cost 1993 1995 1996 Spartan Series addresses all aspects of cost 1997 Majority of cost is back end Assembly Test Overhead Spartan Series Total Cost Management

79. Academy - High Volume FPGAsPage 79 February 1999 Spartan Series vs. Altera 6000/A * A logic cell is a 4 input Look up table and a Flip-Flop ** XL and A represent 3.3V devices for Xilinx and Altera respectively Only 1 device for 5V, 3 devices for 3.3V 5 devices for 5V and 5 devices for 3.3V

80. Academy - High Volume FPGAsPage 80 February 1999 Spartan Series vs. Altera 10K * A logic cell is a 4 input Look up table and a Flip-Flop ** XL and A represent 3.3V devices for Xilinx and Altera respectively Only 2 low density 3.3V devices 5 devices for 5V and 5 devices for 3.3V

81. Academy - High Volume FPGAsPage 81 February 1999 Xilinx Footprint Compatibility Leadership vs. FLEX 6K/A SpartanAltera 6KSpartanXLAltera 6KA 5 Volt 3.3 Volt BG256 PQ240 PQ208 TQ144 VQ100 PC84 S05 S10 S20 S30 S40 6016 6010A 6016A 6024A S05XL S10XL S20XL S30XL S40XL

82. Xilinx Footprint Compatibility Leadership vs. FLEX 10K/A SpartanAltera 10KSpartanXLAltera 10KA 5 Volt3.3 Volt BG356 BG256 PQ240 PQ208 TQ144 VQ100 PC84 S05 S10 S20 S30 S40 10K10 10K20 10K30 S05XL S10XL S20XL S30XL S40XL 10K10A 10K30A REFERENCE:

83. Academy - High Volume FPGAsPage 83 February 1999 SpartanXL Provides Lowest K Factor 2.5V3.3V 5.0V SpartanXL K Factor = 11

84. Spartan Series Collateral oWebLINX http://www.xilinx.com/products/spartan.htm Datasheet: http://www.xilinx.com/partinfo/spartan.pdf —ASIC Replacement http://www.xilinx.com/products/asic.htm oStatus, FAQ on Sales Partner Web http://www.partner.xilinx.com/common/spartan/ oSales Partner Web “Presentations a la Carte” http://www.partner.xilinx.com/common/CustPres oSpartan Sales Guide P/N: 100270 oSpartan/XL vs. Altera FLEX Competitive Alert 10KA P/N: 100432 6K/A P/N: 100429 REFERENCE:

85. Academy - High Volume FPGAsPage 85 February 1999 Other Families

86. Academy - High Volume FPGAsPage 86 February 1999 Older Architectures

87. Differentiating Features XC5200SpartanXC4000E LCs/CLB42.3752.375 RAMNoneSync.Sync./Async. PCINoYesYes DecodeNoNoYes Wired-ANDNoNoYes I/O FFsNoYesYes ConfigExp/Par/Ser SerPar/Ser Packages14616 REFERENCE:

88. Academy - High Volume FPGAsPage 88 February 1999 AppLINX and Data Book Status

89. Academy - High Volume FPGAsPage 89 February 1999 AppLINX CD-ROM oContains WebLINX + Xilinx File Download oWebCD Viewer functionality —Search by categories, including Solution Records —Automatically looks for internet connection and pulls updated files from WebLINX —Alternative: open root index.htm

90. REFERENCE: Customer Presentations on AppLINX o/mcpmat/alacarte.zip opkunzip password: sales oOpen index.htm to see descriptions

91. Academy - High Volume FPGAsPage 91 February 1999 1999 Data Book oSee WebLINX for updated individual datasheets oData Book PDF file available on AppLINX/WebLINX-FTP —Single 7M PDF file for use of Table of Contents and Index, or Acrobat “Find” to search —Also available as individual PDF files, as on WebLINX oPrinted version shipping by 4/99