Chapter 4 Overview of Wafer Fabrication 半導體製程 材料科學與工程研究所 張翼 教授

Figure 4.1 Wafer-fabrication stage.

Figure 4.2 Wafer terminology. 1. chip, die, device, circuits 2. scribe line, saw line, streets, avenues 3. engineering die, test die 4. edge die (as chip gets bigger, need to increase wafer size to reduce edge die ratio) 5. wafer crystal planes 6. major flat / notches

Figure 4.3 Basic wafer-fabrication operations. Layering → thin film layers: evaporation, sputtering, CVD Patterning → photo lithography, photo masking Doping → puts specific amount of dopants in the wafer

Figure 4.4 Cross section of completed metal gate MOS transistor with grown and deposited layers.

Figure 4.5 Layering operations.

Step 1: Layering Operation Step 1: Layering Operation. The building starts with an oxidation of the wafer surface to form a thin protective layer and to serve as a doping barrier : This silicon dioxide layer is called the field oxide. Step 2: Patterning Operation. The patterning process leaves a hole in the field oxide that defines the location of the source, gate, and drain areas of the transistor. Step 3: Layering Operation. Next, the wafer goes to an silicon dioxide oxidation operation. A thin oxide is grown on the exposed silicon. It will serve as the gate oxide. Step 4: Layering Operation. In step 4, another layering operation is used to deposit a layer of polycrystalline (poly) silicon. This layer will also become part of the gate structure. Step 5: Patterning Operation. Two openings are patterned in the oxide / polysilicon layer to define the source and drain areas of the transistor.

Step 6: Doping Operation Step 6: Doping Operation. A doping operation is used to create a n-type pocket in the source and drain areas. Step 7: Layering Operation. Another oxidation / layering process is used to grow a layer of silicon dioxide over the source / drain areas. Step 8: Pattering Operation. Holes, called contact holes, are patterned in the source, gate, and drain areas. Step 9: Layering Operation. A thin layer of conducting metal, usually an aluminum alloy, is deposed over the entire wafer. Step 10: Patterning Operation. After deposition, the wafer goes back to the patterning area where portions of the metallization layer are removed from the chip area and the scribe lines. The remaining portions connect all the parts of the surface components to each other in the exact pattern required by the circuit design.

Step 11: Heat Treatment Operation Step 11: Heat Treatment Operation. Following the metal patterning step, the wafer goes through a heating process in a nitrogen gas atmosphere. The purpose of the step is to “alloy” the metal to the exposed source and drain regions and the gate region to ensure good electrical contact. Step 12: Layering Operation. The final layer of this device is a protective layer known variously as a scratch or passivation layer (not shown in Fig. 4.5). Its purpose is to protect the components on the chip surface during the testing and packaging processes, and during use. Step 13: Patterning Operation. The last step in the sequence is a patterning process that removes portions of the scratch protection layer over the metallization terminal pads on the periphery of the chip. This step is known as the pad mask (not shown in Fig. 4.6)

Figure 4.6 Table of layers, processes, and materials.

Figure 4.7 Patterning. Most critical step in process, 10-20 times during process. Contamination control is important.

Figure 4.8 Doping.-(1) 1000℃ expose wafer to vapors of dopants (chemical process)

Figure 4.8 Doping.-(2) Atoms are ionized, accelerated and sweep across the surface. (physical process)

Figure 4.9 Formation of doped N- or P-type region in wafer surface.

Figure 4.10 Cross section of typical planarized two-level metal VLSI structure showing range of via depths after planarization. (Courtesy of Solid State Technology)

Figure 4.11 Summary of wafer-fab operations/processes.

Figure 4.12 Example functional logic design of a simple circuit. 1. Functional block diagram

Figure 4.13 Example circuit schematic diagram with component symbols.

Figure 4.14 Composite and layer drawings for 5-mask silicon gate transistor. Circuit layout: must consider individual components → material resistivity, individual component size. Use CAD to translate each circuit component into physical shape and size.

Figure 4.15-(1) (a) Chrome on glass reticle one reticle

Figure 4.15-(2) (b) Photomask of same pattern

Figure 4.16 Silicon gate MOS process steps. Fabrication processes

Figure 4.17 Chip terminology. 1. Bipolar Transistor 2. Circuit designation number 3. Bonding Pad 4. Contamination 5. Metallization lines 6. Scribe line 7. Unconnected components 8. Mask align mark 9. Resistor

Figure 4.18 Wafer sort. (Die sort, electrical sort) wafer mount on a vacuum chuck align electrical probe to the Pad. Need to reduce test time to reduce cost.

Figure 4.18 Automatic testing test goals: 1. identify working chip 2. characterization of the device / circuit electrical parameter 3. Feed back over all performance for process improvement and SPC (statistic process control)

Figure 4.19 Integrated circuit manufacturing sequence.