Spartan-II Memory Controller For QDR SRAMs Lobby Pitch February 2000 ®

® Xilinx at Work in High Volume Applications Agenda  Introduction  QDR Architecture Advantages  Xilinx Value Proposition  Spartan-II FPGA Competitive Advantage  Summary

® Xilinx at Work in High Volume Applications Spartan-II FPGAs Are The First Memory Controller Solution For QDR SRAMs Spartan-II Family  An Ideal QDR SRAM Controller Solution —100,000 system gates at under $10 —Extensive features: BlockRAM, DLL, SelectIO (HSTL) —Vast IP portfolio —Provide Density, Features, Performance at ASIC prices —Reprogrammability

® Xilinx at Work in High Volume Applications QDR™ SRAMs  Quad Data Rate (QDR) SRAM —Next generation high-performance SRAM architecture —Targeted for next generation high speed datacom applications –Switches and routers operating at data rates above 200 MHz —Significantly increases memory bandwidth —Two ports independently run at Double Data Rate (DDR), resulting in four data items per clock cycle or QDR —Will serve as the main memory for look-up tables, linked lists and controller buffer memory  Architecture Developed By Cypress, IDT and Micron —May be adopted by other SRAM vendors

® Xilinx at Work in High Volume Applications QDR SRAM Traditional SRAM QDR Simplifies High Speed Design  Separate Inputs and Outputs on QDR SRAMs —Remove possibility of bus contention and simplify designs —Facilitate high frequency design Read & Write Process in QDR & Regular SRAMs

® Xilinx at Work in High Volume Applications QDR Architecture Advantages  Separate I/O —Separate DDR Read and Write ports —Bus contention –Occurs frequently in a networking environments –Occurs when the SRAM drives the data on a read faster than the ASSP can take data off the bus after a write –As operating frequencies increase, bus contention rises dramatically –Separate read & write data buses ensure that bus contention never occurs —Constant flow of data –Requires the bus be turned around for a read & write –Causes non-uniform data flow between controller & SRAM –QDRs provide a higher throughput than common SRAMs

® Xilinx at Work in High Volume Applications QDR Architecture Advantages  Maximum Frequency/Bandwidth —PB-, ZBT- & NoBL SRAMs can run at very high frequencies –But limited due of operating a common I/O data path — QDRs allow Double Data Rate transfers on both the inputs and outputs –Improves throughput through simultaneous read or write  Voltage Migration — I/O pins of QDR SRAMs operate at HSTL voltage levels –At lower voltage levels, there is low-swing, high-speed operation of the inputs and outputs  Simultaneous Read and Write —DDR on two ports provides four data items per clock or QDR

® Xilinx at Work in High Volume Applications The Spartan-II Memory Controller For QDR SRAMs Spartan-II Memory Controller for QDR SRAMs - Block Diagram

® Xilinx at Work in High Volume Applications Spartan-II Competitive Advantage  First and Only Memory Controller Solution for QDR SRAMs  Spartan-II Advantages —High-Speed Transceiver Logic (HSTL) I/O Buffers —Delay-Locked Loops (DLL) —Block SelectRAM —I/O Performance —Core Performance —Availability (first & only solution)

® Xilinx at Work in High Volume Applications SSTL3 GTL+ 5-volt tolerant I/O SDRAM QDR SRAMs MIPS  P 2x CLK PCI Clock Mgmt - Board deskew PLL $7.50 PCI Master/ Target Controller $15 SSTL-3 Translators $4 FIFOs Memory Dual Ports $7$2 PCI-MIPS System Controller $40 $6 GTL+ Backplane Drivers HSTL Translators $6 Spartan-II: High Volume System Integration

® Xilinx at Work in High Volume Applications 40K $10 Spartan-XL Spartan-II Syste m Gates Spartan-III 30K 250K 100K Driving Down The Cost of FPGAs

® Xilinx at Work in High Volume Applications Additional Support For Xilinx Solutions  Xilinx At Work Website Contains Detailed Information —Market Overview —Glossary —Applications Notes —White Papers —Lobby Pitch —Reference Designs —FREE VHDL CODE  FPGA Strategic Applications Group —System level expertise for Xilinx At Work vertical markets

® Xilinx at Work in High Volume Applications Summary  QDR SRAM Architecture is Being Accepted as the Memory Standard for Next Generation Data Networking Applications  The Spartan-II Family Brings Significant Advantages as a QDR SRAM Memory Controller: —Features (DLL, HSTL I/O Buffers, Block SelectRAM) —Performance (200MHz clock speeds) —Scalability and Flexibility —Cost Effectiveness —Availability (first & only solution)