1. “With 1 MB RAM, we had a memory capacity which will NEVER be fully utilized” - Bill Gates

2. DRAM read operations  Take the word line HIGH.  Detect whether current flows into or out of the cell.  Note: cell contents are destroyed by the read!  Must write the bit value back after reading.

3. DRAM write operations  Take the word line HIGH.  Set the bit line LOW or HIGH to store 0 or 1.  Take the word line LOW.  Note: The stored charge for a 1 will eventually leak off.

4. Access time of high-speed DRAM Access time of DRAM can be divided into the following two types: Random access time : Access time in which both the row address and the column address different from those of the preceding cycle are accessed. Burst access time : Access time in which the same row address and a column address different from that of the preceding cycle are accessed.

5. About Pipeline Burst  Purpose: Minimizes wait states so that memory can be accessed as fast as possible by the microprocessor  How?  A burst mode that pre-fetches memory contents before they are requested  pipelining so that one memory value can be accessed in the cache at the same time another memory value is accessed in DRAM

6. TYPES OF DRAM

7. SDRAM is a type of DRAM which operates in synchronization with input clock. This system has been developed from the idea that the synchronization of the system clock and the operating clock of a memory will make it easier to control each other.

8. Features of SDRAM The following explains the features of SDRAM. (1) Synchronous operation SDRAM latches each control signal at the rising edge of basic input clock and inputs/outputs data in synchronization with the clock signal. Controls are made easier by synchronizing the clock with the system memory clock. (2) Controls with commands A command is a combination of logic levels of control signals. Typical commands include active command, read or write command, precharge command, etc. The conventional DRAM is also controlled with combinations of logic levels of control signals. The conventional DRAM, however, does not have the concept of command.

13. FPM  Fast Page Mode RAM  Traditional RAM for PCs  Hard to find and more expensive  Access Times are 60 to 70 ns.  Allows faster access to data on the same page EDO  Extended Data Output  Faster than conventional DRAM and FPM  Cheaper  Copies an entire block of memory to its internal cache, while the processor is accessing this cache the memory can collect a new block to send  EDO can access data faster if the cache controller supports PIPELINE BURST

14. Synchronous DRAM Runs on much higher clock speeds than conventional memory Supports bus rates up to 100 MHz Expensive

15. SDRAM Variations  Regular SDRAM  Runs at same speed as system bus  Width of data path: 64 bits (50% faster than its predecessor, EDO memory)  SDRAM II (DDR) or DDRAM or DDR SDRAM  Runs twice as fast as regular SDRAM and doubles the rate of memory  Width of data path: 64 bits  SyncLink (SLDRAM)  Increases number of memory banks that can be accessed simultaneously from four to sixteen

16.  DDR SDRAM  reads data on both the rising and falling edges of the clock signal  data is read twice as fast  instead of 133mhz, it can do speeds of 266mhz  Rambus DRAM  Can transfer data at up to 800 MHz  Sends less data at a time but more frequently  also reads data on both rising and falling edges of the clock cycles

17.  RDRAM  Rambus Dynamic Random Access Memory  Technology developed and licensed by the Rambus Corporation  At a RAM speed of 800 megahertz (800 million cycles per second), the peak data transfer rate is 1.6 billion bytes per second.  An alternative to SyncLink DRAM (SLDRAM)

19. EDO DRAM (Extended Data Out DRAM) EDO DRAM is a still faster version of FPM DRAM. If the data output (read cycle) of FPM DRAM is made higher speed, the data output time becomes shorter. Since EDO DRAM is provided with extended output functions, the data output time does not become short even in higher speed. Thus, wider range for the timing can be allowed in the data output side, and as a result a speed higher than that of FPM DRAM can be realized. In addition, since EDO DRAM and FPM DRAM are compatible DRAM that have packages with the same pin configuration, EDO DRAM can easily replace FPM DRAM. In the middle of 1996, EDO DRAM represented approximately 50% of all the DRAM shipment.

20. SDRAM (Synchronous DRAM) Specifications different from those of the conventional DRAM are used for SDRAM to realize higher-speed operation. EDO DRAM is provided with extended output functions, but it has a problem of operating frequency similarly to FPM DRAM if higher speed is demanded. Generally, EDO DRAM can be synchronized only up to the clock of approximately 75 MHz. SDRAM is capable of operation at higher operating frequency than EDO DRAM is. SDRAM, however, has package pin configuration, control signal names, and the number of signals different from those of the conventional DRAM since SDRAM performs controls with an interface different from that of the conventional DRAM and the new specifications.

21. RDRAM (Rambus  DRAM) RDRAM employs the unique specifications proposed by Rambus Inc. Although RDRAM operates in synchronization with the clock of 300 MHz, adoption of the dual edge system makes it equivalent to synchronization with the clock of 600 MHz. The dual edge system is a system that can perform controls at two points: the rising edge and the falling edge of one clock. While the operating frequency of RDRAM is currently 300 MHz, DirectRDRAM aims at 400 MHz. DirectRDRAM has the highest operating frequency of all the high-speed DRAM.

22. DDR SDRAM (Double Data Rate SDRAM) DDR SDRAM is a synchronous DRAM that realizes high-speed data transfer while taking over the specifications of SDRAM as much as possible. Although DDR SDRAM does not have complete compatibility with SDRAM, DDR SDRAM can be used with simple specification changes of the SDRAM controller since DDR SDRAM has basically the same package pin configuration and the control method as SDRAM. While SDRAM adopts the single-edge system, which performs controls at a single edge of the basic clock, DDR SDRAM adopts the dual-edge system.

23. FPM DRAM, EDO DRAM, SDRAM, and RDRAM have approximately equal random access times but have different burst access times.