MICE Tracker Readout Status VLPC – Cryo – Front End Electronics A.Bross Berkeley, February 2005

Analog Front End Board for VLPC Readout 9 o K VLPC (x512) AFE DISCRADC Discriminator output every 396 nsec for L1 Amplitude signal readout for L3 and offline 8 photons 50 fC Central Fiber Tracker cylinder

 First AFEII prototype is now on the cryostat and taking data.  Next 4 slides show the AFEI problems that AFEII is designed to solve: u SVX saturation. u SVX tick to tick ped variation. u DISCR to SVX data cross talk. AFEII prototypes

AFEII proto: Results  Biggest concern is SVX saturation  Test: inject huge LED pulse, (7V, 80ns) measure small pulse in the same superbunch 3pe in xing 20 -> readout > 100pe in xing 5 Picture from AFEI

AFEII proto: Results  Tick to tick variation in pedestals. u Reset is identical every xing, so there is none. The sum of data from xing 5, 8, 11, 14, 17, 20 all 64ch from module 1 PMR: I included the individual xing plots in spare slides section, if you wish to check in more detail.

AFEII proto: Results  Discr to ADC xtalk: it is impossible to make a plot like this with AFEI Plot from AFEII with 30% discr occupancy. Compare to AFEI with 32% discr occupancy one chan…

AFEII proto: Results  Discr to ADC xtalk: it is impossible to make a plot like this with AFEI Plot from AFEII with 30% discr occupancy. Compare to AFEI with 32% discr occupancy many chan…

4) AFEII-t design  Was on hold until AFEII prototype was up– now starting integrate lessons from AFEII prototypes.  Stefano Rapisarda is joining this effort.

AFE II/AFEIIt Status  Recently concluded Dzero internal review u awaiting report/recommendations of the committee  Progress on a number of fronts: 1. AFEII on the cryostat and taking data. (same cass. as used for AFEI studies by Juan and Peter) 2. Better understanding of TriP-t, studies in progress, needed manpower now on board. 3. AFEII-t engineering help identified and on board.

Trigger Pipeline Chip with Time Stamp Tript

Currents to opamps, switch settings, feedback settings set with on-chip DACs To date, parameters are based on what worked on the TRIP chip Adjustment of these parameters could improve performance further 200f 1.5p 4.0p

Digital (DISC) out

 Saturation occurs ~130fC; expected at ~90fC  Residual seems related to DC level of ~40mV which also appears on T_OUT. Suspicion rests upon output drivers to analog pipeline  Chip designer has recently suggested a “parameter” change that he believes will help  Might make identification of individual p.e. peaks harder (?)  Noise is ~3mV Gaussian, shown as error bars on plot and is the same for the T_OUT line 8 40k gain 16 p.e. 1 p.e. A- pulse

Does t affect A ? 100fC at “Sweet spot” 30fC, 60nsec later

Does t affect A ? Existence of analog time-info pulse lowers the analog amplitude-info pulse by 3 1 / 2 ~ 4 % of the size of the time-info pulse Same if time-info pulse lowered by changing the actual time or by changing the current integrated to measure the time Ratio of pulses from adjacent fibers with similar time data sees smaller effect than individual pulses will

Pulse Time (T_OUT) Adjustment of current through integrating circuit permits gains ranging from ~2 to ~20 mV/ns t - pulse mV

Time Walk  t /  Q  0.40 mV/fC, corresponding to  44 ps/fC T_OUT has large pulse-to-pulse fluctuations below ~20fC  2 gain over threshold Digital discriminator set to fire ~4f in this test Only been able to look carefully at 2 channels so far, but they are similar Noisy Data A MIP at 90  corresponds to about 50fC (8 photoelectrons collected)

What Happens Next  Impact of A -pulse nonlinearity should be quantitatively assessed, should test with “parameter” change not solve the problem  Chip order in early March will probably be submitted with multiple versions, so it would be prudent to have older pipeline output driver, or other redesign, as one of them - should not impact schedule  Further probing of parameter space will provide info re. optimal running conditions  Documentation needed

TriPt - Conclusions  TriP-t is fully fuctional and basically performs as expected  Answers to specific questions:  t -info pulse lowers A -info pulse 3 ½ ~ 4% of t -pulse; effect on A ratio in adjacent fibers ought to be even smaller u Time pulse gain setable from 2 ~20 mV/ns u Time output walk ~44 ps/fC for pulses with ~2 or more p.e.  Further work is warranted for:  A -pulse nonlinearity  Optimization of parameter space  Documentation

LVSB Board VME LVDS SERDES Buffer (Serializer-Deserializer)

VME LVDS SERDES Buffer (VLSB)  The D0/MICE VME64 LVDS SERDES Buffer (D0 VLSB) is a VME64 single wide 6U module SERDES (SERializer- DESerializer)  It can be used for Read out and testing the AFEII boards. The module is a custom LVDS  SERDES Buffer with 4 LVDS inputs channels and can be operated stand-alone with minimal additional hardware.  The design allows system expansion to multiple modules.  A D0 VLSB module can receive/generate trigger signals over two Lemo connectors on the module front panel.  A normal test system configuration consist of a VME 64 subrack where slot 1 is occupied by a VME subrack controller and the D0 VLSB cards will occupy one or more of the remaining slots.

VME LVDS SERDES Buffer (VLSB)  The Boards (6) are now complete and ready for test and integration into the MICE DAQ system (KEK and final system if we choose to do so)

VLSB System Architecture  The VLSB standalone system can be expanded to a set of several cards hosted by 6U VME64Xsubrack.  In this case, the cards can be individually accessed though their RS-232 interfaces. A set of four module can be synchronized through the use of the front panel board-to-board connectors.  All cards in the system can be accessed through a VME subrack controller that can be hosted in the subrack slot 1. This controller can provide the VLSB cards with additional interfaces to the outside world (Ethernet, MIL-STD 1553,...).

Board Block Diagram

VLSB – AFEIIt Interface

Data Rate Capabilities  Roughly 200 MB/sec per LSVB board  VME64X standard transfer speed - to 160 Mbytes/sec.  With chosen FPGA, for MICE this system should accommodate muon rates up to 1000 per RF flat top.

VLPC Cryo Status Cryo-Cooler Version

Preliminary fit up - good

Status Summary  Real assembly should start this week.  Many miscellaneous parts ordered and most here. (o- rings, bolts, cryo grease, fittings, copper strips)  Compressor for Cryo cooler wired up. Extending control cables.  Run Cryo cooler only – week of 2/21?  Cool cassettes – week of 2/28 or later?  Ship in March

Pictures – Assembly stand

Issues still to address  Control system details u Sensors, controllers, heater, feed thru’s  Safety Documents & approval u “Pressure vessel” is special u Need to size & obtain relief valves  Thermal link fabrication unknowns  Temperature & pressure stability u small gas volume u part of commissioning/test

Schedule details