Patrick Coleman-Smith CCLRC Daresbury 1 AGATA Digitiser Summary February 2005 Patrick J. Coleman-Smith For the Digitiser Technical Group  I.Lazarus Daresbury  P.MedinaIReS  R.Baumann IReS  C.Santos IReS  M.Chambit IReS  J.Thornhill Liverpool  D.Wells Liverpool

Patrick Coleman-Smith CCLRC Daresbury 2 Revised Mechanical Structure Global Clock internal delivery Laser link trial report TNT2 tests Slow Control Cost Schedule Some Remaining Questions

Patrick Coleman-Smith CCLRC Daresbury 3 Previous Mechanical Structure

Patrick Coleman-Smith CCLRC Daresbury 4 New Mechanical Assembly Mechanical Constraints Distance to the Detector 5 Metres Power Dissipation around 400W Mechanically dependant on the detector array.  Use Water Cooling New arrangement of PCBs

Patrick Coleman-Smith CCLRC Daresbury 5 Structure of the Digitiser: Cooling, and mechanics

Patrick Coleman-Smith CCLRC Daresbury 6 Internal Global Clock Distribution Clock reference input from the Pre- Processor core board using Laser link. The idea is to use Sinusoidal clock through a Jitter smoother and a Mini-circuit splitter Distribute to the Flash ADCs via cable. Passive Filter to transform the square wave input to a sinusoidal signal

Patrick Coleman-Smith CCLRC Daresbury 7 Internal Global Clock distribution schematic Under Development at Liverpool University

Patrick Coleman-Smith CCLRC Daresbury 8 Laser Trial Test and Results Designed the Laser Trial board with four Laser modules. Used Xilinx recommended PCB connection parameters for the 2Gbit/sec connections from the Virtex2Pro BGA to the Laser modules. Test connection to a Xilinx Development board:  16 bit data from counter incrementing at 100Mhz  Three channels operating independently.  Receiver tracks the data, checking each value received.  Transmitter and receiver share the same clock. Ran for 8 days with no errors.  6.9 x Transfers per link

Patrick Coleman-Smith CCLRC Daresbury 9 Laser Trial Test Block Diagram

Patrick Coleman-Smith CCLRC Daresbury 10 Laser Trial Board Laser Transmitter Virtex2Pro 100Mhz clock input Analog Inspection

Patrick Coleman-Smith CCLRC Daresbury 11 Laser Trial Setup

Patrick Coleman-Smith CCLRC Daresbury 12 TNT2 Tests 1

Patrick Coleman-Smith CCLRC Daresbury 13 TNT2 Tests 2

Patrick Coleman-Smith CCLRC Daresbury 14 Slow Control External interfaces: Xport module Galvanically isolated serial link over 10/100baseT physical layer. Experiment control for the digitiser. Laboratory and diagnostic access. Internal interfaces : Serial link Link is Clock, Data, Frame signals Simple protocol developed at Liverpool.  Connects all FPGAs using Star topology.  Requests all generate an Acknowledge.  Timeout with reset of link.  Long write to allow re-program of FPGA.

Patrick Coleman-Smith CCLRC Daresbury 15 Prototype Digitiser : 45,000 Euros Further Digitisers: 30,000 Euros Cost Estimates

Patrick Coleman-Smith CCLRC Daresbury 16 Schedule

Patrick Coleman-Smith CCLRC Daresbury 17 Some Remaining Questions 1. Offset Control link protocol 2. Segment and Core data link start-up protocol, and how to respond to failures. 3. Global clock link start-up and calibration 4. Pre-Amp Interface - Pulser Control 5. Slow Control External interface protocol 6. Mechanical mounting on the Apparatus

Patrick Coleman-Smith CCLRC Daresbury 18 Signal interconnections

Patrick Coleman-Smith CCLRC Daresbury 19 Front panel clock interconnects

Patrick Coleman-Smith CCLRC Daresbury 20 Main Structure of the digitiser housing

Patrick Coleman-Smith CCLRC Daresbury 21 Block Diagram of the Digitiser

Patrick Coleman-Smith CCLRC Daresbury 22 Segment board block diagram

Patrick Coleman-Smith CCLRC Daresbury 23 DC-DC graphs

Patrick Coleman-Smith CCLRC Daresbury 24 Clock Test boards

Patrick Coleman-Smith CCLRC Daresbury 25 Slow control test board