International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Model Proposals For Public 07/13/05 Conference (based on Rev1Kc, 07/12/05)

ORTC Overview - 2005 ITRS Proposals Recommendation for one standard TWG table technology trend header Presently continue to use DRAM stagger-contacted M1 as typical industry lithography driver – UNCHANGED from the 2003/2004 Roadmap Update Remove ITRS single-product “node” label emphasis, to minimize industry guidance confusion; as we transition to product-oriented technology trend drivers and cycles* ORTC Table 1a,b - adjusted to Proposed Japan (STRJ) MPU/ASIC M1 Half-Pitch Trend Stagger-contacted, same as DRAM 2.5-year Technology Cycle* (.5x/5yrs) 180nm/2000; 90nm/2005; 45nm/2010(equal DRAM) Then continue on a 3-year Technology Cycle*, equal to DRAM 2010-2020 ORTC Table 1a,b - added Proposed STRJ Flash Poly (Un-contacted dense lines) 2-year Technology Cycle* (0.5x/4yrs) 180nm/2000; 130nm/2002; 90nm/2004; 65nm/2006 Then 3-year Technology Cycle* 1 year ahead of DRAM ’06-’20 ORTC Table 1a,b – adjusted MPU/ASIC Printed Gate Length to FEP and Litho TWG agreement for ratio relationship to Final Physical Gate Length, which remains UNCHANGED from the 2005 ITRS targets (3-year cycle* after 2005) TWG table Product-specific technology trend driver header items to be added to individual TWG tables from ORTC Table 1a&b Chip Size Models connected to proposals and historical trends, incl. new Flash Model Function Size [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)] Functions/Chip [Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU] Chip Size [hp MPU; cp MPU; DRAM; Flash] *Note: Cycle = time to 0.5x linear scaling every two cycle periods ~ 0.71x/ cycle DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

2003/2004 ITRS Definition of the Half Pitch - WAS Source: 2003 ITRS - Exec. Summary Fig 4 2003/2004 ITRS Definition of the Half Pitch - WAS [DRAM half-pitch determines the 2003 ITRS “node”] Metal Pitch Typical DRAM Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 Poly Typical MPU/ASIC Un-contacted Poly MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2 Contacted Metal 1 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Metal 1 (M1)

2005 Definition of the Half Pitch – IS [No single-product “node” designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables] Metal Pitch Typical DRAM/MPU/ASIC Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Poly Typical flash Un-contacted Poly FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2 8-16 Lines

Fig 2 Production Ramp-up Model and Technology Node -24 12 24 -12 Volume (Parts/Month) 1K 10K 100K Months -24 1M 10M 100M Alpha Tool 12 24 -12 Development Production Beta First Conf. Papers First Two Companies Reaching Production Volume (Wafers/Month) 2 20 200 2K 20K 200K Source: 2003 ITRS - Exec. Summary Fig 2 Fig 2 [UNCHANGED]

Source: 2003 ITRS - Exec. Summary hp22 hp32 hp45 hp65 hp90 2018 2016 2015 2013 2012 2010 2009 2007 2006 2004 2003 2002 [Actual] Year of Production hp130 Technology Node (nm) WAS: 2003 ITRS Technology Nodes: 3-year cycle* 3-Year Technology Cycle 2-Year Technology Cycle [1998-2002actual] Note: Faster introduction of half-poly pitch from Flash is expected; and Doubling of transistors every 2 years from MPU/ASIC is expected. * Cycle Time = one-half of the time to reach a technology trend reduction to 0.5x Source: 2003 ITRS - Exec. Summary

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Note: Faster introduction of half-poly pitch from Flash is expected; Doubling of transistors every 2 years from MPU/ASIC is expected 2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 1yr ahead of DRAM @65nm/’06 3-Year Technology Cycle 2-Year Technology Cycle [’98-’06 ] Year of Production Technology - Uncontacted Poly H-P (nm) 2003 2005 2001 65 22 32 45 16 2008 2006 2002 [Actual] 2004 2000 90 130 180 76 107 151 50 57 13 2015 2012 2009 2018 2016 2013 2010 2019 2020 2005 ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal DRAM @45nm/2010 Technology - Contacted M1 H-P (nm) 157 136 119 103 78 68 59 52 [July’08] [July’02] [130] [ 65] 2007 2.5-Year Technology Cycle 3-2-Yr Cycle] 14 IS: 2005 (’05-’20) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle 2-Year Technology Cycle [‘98-’04] 80 71 10 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

2005 ITRS Product Technology Trends .71x/2.5yrs Historical .71x/3yrs 2005 ITRS Product Technology Trends Past   Future 2005 - 2020 ITRS Range [Cross DRAM 65nm/2006 1 year ahead after that] [Equal DRAM 45nm/2010] [GLpr IS = 1.6818 x GLph WAS, which is unchanged from 2003/04 ITRS, but under discussion by FEP, PIDS, Litho, and Design TWGs for CD-control red limits] [Unchanged from 2003 ITRS] .71x/2yrs GLpr / GLph = 1.6818 Ratio DRAM Survey Update: - DRAM (H-P unchanged) Flash: Japan/STRJ MPU: Japan/STRJ

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Past   Future 2005 - 2020 ITRS Range DRAM IS: 8f2 -> 6f2 / 2008 5f2 ~ 29f2 ~ 320f2 Flash 28f2 -> 4f2 [WAS: 2003 ITRS] [IS: 2005 ITRS] Note: f = product-related Half-Pitch Feature Size; A = product-related Design Factor; n = # transistors per SRAM cell or MPU Logic Gate; Af2 = Function Size; Af2/n = SRAM Cell or Logic Gate Transistor Size Note for Flash: SLC = Single-Level-Cell Size MLC = Multi-Level-Cell (Electrical Equivalent) Cell Size DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

Moore’s Law After 40 years (functions per chip) 4004 8080 8086 8008 Pentium® Processor 486™ DX Processor 386™ Processor 286 Pentium® II Processor Pentium® III Processor Itanium® Processor Pentium® 4 Processor Itanium® 2 Processor 2X/2YR 2X/1YR Source: Intel® Corp. Moore’s Law states that the number of trasistors that can be crammed onto a chip will double every two years. Intel’s microprocessors have followed this trend for over 3 decades! Our latest Itanium® 2 processor, codenamed Madison, contains over 400 million transistors. We expect to have a 1 billion transistor microprocessor in the early part of the 2nd half of this decade.

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Chip Size Trends – 2005 ITRS Functions/Chip Model Proposal IS (WAS) Past   Future 2005 - 2020 ITRS Range Average Industry 1970-2020 “Moore’s Law” 2x Functions/chip Per 2 years (@Volume Production, Affordable Chip Size**) ** Affordable Production Chip Size Targets: DRAM, Flash < 145mm2 hp MPU < 310mm2 cp MPU < 140mm2 ** Example 1.1Gt P07h MPU @ intro in 2004/620mm2 @ prod in 2007/310mm2 0.39Gt P07c MPU @ intro in 2004/280mm2 @ prod in 2007/140mm2 MPU ahead or = 2x Xstors/chip Thru 2010 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Past   Future 2005 - 2020 ITRS Range Chip Size Trends – 2003/04 vs.2005 ITRS DRAM & Flash (NEW) Model IS DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Past   Future 2005 - 2020 ITRS Range Chip Size Trends – 2003/04 vs.2005 ITRS Flash (NEW) Model IS DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Past   Future 2005 - 2020 ITRS Range Chip Size Trends – 2005 ITRS MPU Model Proposal IS DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Summary DRAM Model stagger-contacted M1 is unchanged from 2003/2004 Update ITRS (single-“Node” reference removed) MPU Revised M1 to stagger-contact half-pitch (same as DRAM) and 2.5-year cycle* through 2010, then 3-year cycle* same as DRAM New Flash Model Added for un-contacted poly half-pitch and equal to DRAM contacted, but continues on 2-year cycle* to 1 year ahead of DRAM in 2006, then 3-year cycle* same as DRAM Printed MPU/ASIC Gate Length adjusted to new FEP and Litho TWGs ratio agreement, but Physical GL unchanged and on 3-year cycle* beginning 2005 Historical chip size models “connected” to new Product model proposals, including design factors, function size, and array efficiencies Average industry product “Moore’s Law” met or exceeded throughout 2005-2020 ITRS timeframe [* ITRS Cycle definition = time to .5x linear scaling every two cycle periods] DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

Backup

Generic ITRS Table Header Technology Trend Proposal: Optional (from ORTC Table 1a&b) TWG Table Product-Specific Technology Trend Proposals: