1. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Interconnect Working Group ITRS 2005 13 July 2005 San Francisco

2. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Agenda Membership Scope and cross section Key issues MPU Half Pitch Cu resistivity effects Crosstalk Low k comments DRAM Summary

3. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Japan Tomoji Nakamura Hideki Shibata Taiwan Douglas CH Yu US Robert Geffken Christopher Case Europe Hans-Joachim Barth Alexis Farcy Korea Hyeon-Deok Lee Hyun Chul Sohn ITWG Regional Chairs

4. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Participants Robert Geffken Hans-Joachim Barth Alexis Farcy Harold Hosack Paul Feeney Ken Monnig Rick Reidy Hideki Shibata Kazuyoshi Ueno Michele Stucchi Douglas Yu Ming-Shih Yeh Osamu Yamazaki Lucile Arnaud JD Luttmer Brongersma Sywert Ivan Berry Manfred Engelhardt Dirk Gravesteijn NS Nagaraj Mike Mills Gunther Schindler Chung-Liang Chang Tomoji Nakamura Christopher Case

5. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Interconnect scope Conductors and dielectrics –Metal 1 through global levels –Starts at pre-metal dielectric (PMD) Associated planarization Necessary etch and surface preparation Embedded passives Reliability and system and performance issues Ends at the top wiring bond pads Predominantly needs based, with some important exceptions ( and resistivity)

6. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

7. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

8. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Technology Requirements Wiring levels including optional levels Reliability metrics Minimum wiring/via pitches by level Performance metric Planarization requirements Conductor resistivity Barrier thickness Dielectric metrics including effective Crosstalk figure of merit

9. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Recent publications by logic device manufacturers suggest that M1 pitch and intermediate wire minimum pitch are scaling at a rate faster than the 2004 ITRS Non-contacted or staggered contacted M1 pitch is widely used by most logic manufacturers. To avoid ambiguity - we will use staggered contacted M1 half pitch. Changes: –90 nm M1 half pitch in 2005 –scaling at x 0.75 / 2 years from 2005 to 2009 –reverting to 3 years cycle in 2010 and beyond Metal 1 pitches converging between DRAM, logic, flash Whose linewidth is it anyway? The pitch for M1

10. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Source: 2003 ITRS - Exec. Summary Fig 4 Fig 4 Metal Pitch Typical DRAM Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 Poly Pitch Typical MPU/ASIC Un-contacted Poly MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2 Typical MPU/ASIC Contacted Metal 1 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Metal 1 (M1) Pitch - Staggered contacted M1 pitch same as DRAM - Staggered contacted M1 pitch same as DRAM Half Pitch Definition

11. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 - 90nm half pitch in 2005 and 75% shrink/2years - Scaling rate relaxed to 70%/3years same as DRAM after 2010 M1 half pitch

12. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Size matters 2003 – the impending impact of Cu resistivity increases at reduced feature sizes (due to scattering) - noted 2004 – metrics introduced to highlight the impact of width dependent scattering on the effective resistivity and impact on RC delay For 2005- –Models have been refined using data to more accurately predict the resistivity due to changes in aspect ratio, shape metal thickness, and grain boundary scattering –Metrics have been recalculated Adapt the same methodology for DRAM when Cu is introduced (2007)

13. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Size matters Courtesy: Infineon Technologies Copper resistivity o = constant 1.8 -cm at 300 K A mean free path of charge carriers =3.4×10-6 cm A wire width W (cm) A probability for reflection of electrons at the grain boundaries of 0.19 The portion, p=0.33 of electrons specularly reflected from the walls (surface or interface).

14. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Impact of scattering on line resistivity From discussion with Design TWG Resisitivity rise not a problem for M1 May be yellow issue for intermediate levels at/after 45nm

15. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Aspect Ratio Dependence Courtesy: Infineon Technologies

16. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Interconnect performance: crosstalk Crosstalk among neighbouring interconnects –Capacitive crosstalk roughly proportional to c = C IMD / C ILD Mainly fixed by the aspect ratio of lines and vias Crosstalk level increases at each new generation –Induces delay uncertainty (delay increased by crosstalk up to 3x delay) Crosstalk is becoming a major issue Special attention should be paid on these parasitic effects Crosstalk level Input signal Metal 1

17. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Crosstalk Raise awareness of crosstalk issues –Introducing a crosstalk metric to raise visibility of this issue –Potential solutions Introduction of ULK materials Only a slight impact on crosstalk as both C IMD and C ILD decrease Development of hybrid architectures Strong reduction of crosstalk level Ultimate hybrid architecture is air gap Reduction of the k-value of additional capping layers Low-k dielectric barriers Self-aligned barriers

18. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 65 nm example of effective calculation for Realistic and Aggressive Structures StructureHomogeneousHomo w/HMHybrid (Cu D.B) 4.0 (Hardmask) NA3.0 (via) 2.72.52.4 (trench) 2.72.5 eff 2.962.872.83 StructureHomogeneousHomo w/HMHybrid Cu D.B height[nm]35 Hardmask height [nm]NA40 Via height [nm]112 Trench height [nm]126 Minimum L/S [nm]70 Aggressive case in 2007 Realistic case in 2007 StructureHomogeneousHomo w/HMHybrid (Cu D.B) 4.0 (Hardmask) NA3.0 (via) 2.52.3 (trench) 2.52.3 eff 2.782.72 Same thickness at same generation but different materials with various structures value range

19. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Low again! Near Term This is the first dielectric acceleration in 4 years Recognizes renewed interest in ULK and potential solution to integration challenges

20. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Low again! Long Term No known solutions for the long term bulk dielectric materials

21. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 From low to no - air gaps Introduction of air gap architectures –Creation of air gaps with non-conformal deposition –Removal of sacrificial materials after multi-level interconnects Values of effective k-value down to 1.7 with low crosstalk levels Localized air gaps to maintain good thermal and mechanical properties Ultra-low and Air gap ( <2.0) (CVD & Spin-on) Non-conformal deposition Sacrificial material

22. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 DRAM Small changes in specific via and contact resistivity Contact A/R rises to >20 in 2020 - a red challenge - associated with 16 nm DRAM half pitch Low in 2003 - Cu delayed to 2007 Identified need to distinguish embedded, flash, and traditional DRAM

23. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Metal 1 design rule concerns –Staggered pitch used for definition - agreed –New 90 nm half pitch for 2005 - agreed High performance MPU pitches scaling at ~0.75/2 years until 2009 Returning to 0.7/3 years Local wiring pitches for logic, DRAM and SRAM will converge ~ 2010 and follow a common 3 year trend Intermediate and local wiring pitches will also merge similarly ~ 2010 2005 last words

24. Work in Progress --- Not for Publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 Last words Continued changes in materials Must manage 3D CD System level solutions must be accelerated to address the global wiring grand challenge –materials solutions alone cannot deliver performance - end of traditional scaling –integrated approach with design and packaging For 2006 –preparing 3D IC interconnect roadmap –Quantifying emerging interconnect potential solutions