1. 24 July 2002 Work In Progress – Not for Publication PIDS Key Issues for 2002 and 2003 ITRS ITRS Open Meeting July 24, 2002 San Francisco

2. 24 July 2002 Work In Progress – Not for Publication PIDS Scope PIDS = Process Integration, Devices, and Structures Deals with –Process integration and full process flows –MOSFET and passive devices and structures –Device physical and electrical characteristics and requirements –Reliability Subcategories –Memory and logic –Mixed-signal devices –Reliability –Also includes Emerging Research Devices Section (new in 2001 ITRS)

3. 24 July 2002 Work In Progress – Not for Publication Proposed Changes in 2002 PIDS Chapter Low Standby Power (LSTP) technology requirements: physical gate length scaling is slowed by one year compared to 2001 ITRS (see dark boxes, next few slides) –As a result, performance and power dissipation scaling are slowed –This more accurately reflects real LSTP technology scaling Other changes are relatively minor –Updates –Clearer explanations in the notes and wording Major changes, issues will be dealt with in 2003 ITRS

4. 24 July 2002 Work In Progress – Not for Publication LSTP Proposed Changes for 2002: Near-term

5. 24 July 2002 Work In Progress – Not for Publication LSTP Proposed Changes for 2002: Near-term Was LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 4.614.412.962.682.512.321.81 Is LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 5.024.843.313.122.832.662.01 Was LSTP relative device performance [10] 11.051.61.71.8 2 2.6 Is LSTP relative device performance [10] 11.041.521.611.771.892.50 Was Energy per (W/L gate =3) device switching transition (C gate *(3*L gate )*V 2 ) (fJ/device) [11] 0.4480.3810.2770.2040.1630.1230.095 Is Energy per (W/L gate =3) device switching transition (C gate *(3*L gate )*V 2 ) (fJ/device) [11] 0.5420.4710.3570.2920.2160.1720.122 Was Static power dissipation per (W/L gate =3) device (Watts/device) [12] 3.20E-132.90E-132.30E-131.90E-131.60E-131.30E-131.10E-13 Is Static power dissipation per (W/L gate =3) device (Watts/device) [12] 3.60E-133.24E-132.70E-132.34E-131.91E-131.62E-131.22E-13 Year of Production 2001200220032004200520062007 DRAM ½ Pitch (nm)13011510090807065 MPU / ASIC ½ Pitch (nm)15013010790807065 MPU Printed Gate Length (nm)90756553454035 MPU Physical Gate Length (nm)65534537322825 Was Physical gate length low-standby power (LSTP) (nm) [1] 90756553453732 Is Physical gate length low-standby power (LSTP) (nm) [1] 100907565534537 1.6–2.01.4–1.81.2–1.6 Table 36c Low Standby Power (LSTP) Technology RequirementsNear-term

6. 24 July 2002 Work In Progress – Not for Publication LSTP Table Proposed Changes for 2002: Long-Term

7. 24 July 2002 Work In Progress – Not for Publication LSTP Table Proposed Changes for 2002: Long-Term Year of Production201020132016 DRAM ½ Pitch (nm)453222 MPU / ASIC ½ Pitch (nm)503525 MPU Printed Gate Length (nm)251813 MPU Physical Gate Length (nm)18139 Was Physical gate length low-standby power (LSTP) (nm) [1] 221611 Is Physical gate length low-standby power (LSTP) (nm) [1] 282016 0.9-1.30.8-1.20.7-1.1 Table 36d Low Standby Power (LSTP) Technology RequirementsLong-term Was LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 1.430.910.66 Is LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 1.691.050.82 Was LSTP relative device performance [10] 3.25.17 Is LSTP relative device performance [10] 2.974.786.15 Was Energy per (W/L gate =3) device switching transition (Cgate*(3*Lgate)*V 2 ) (fJ/device) [11] 0.0470.0240.014 Is Energy per (W/L gate =3) device switching transition (Cgate*(3*Lgate)*V 2 ) (fJ/device) [11] 0.0710.0340.025 Was Static power dissipation per (W/L gate =3) device (Watts/device) [12] 2.00E-133.00E-13 Is Static power dissipation per (W/L gate =3) device (Watts/device) [12] 2.52E-133.78E-134.32E-13

8. 24 July 2002 Work In Progress – Not for Publication Proposed Changes in 2002 PIDS Chapter Low Standby Power (LSTP) technology requirements: physical gate length scaling is slowed by one year compared to 2001 ITRS (see dark boxes, next few slides) –As a result, performance and power dissipation scaling are slowed –This more accurately reflects real LSTP technology scaling Other changes are relatively minor –Updates –Clearer explanations in the notes and wording Major changes, issues will be dealt with in 2003 ITRS

9. 24 July 2002 Work In Progress – Not for Publication Key 2003 PIDS Issues DRAM: re-evaluate scaling – half pitch, cell size and cell size (a) factor, number of bits per chip, word line voltage –Survey has been sent out: what is in production in 2002, plans beyond 2002 NVM flash and FeRAM: changes in scaling of half pitch, cell size and cell size factor contemplated for 2003 Reliability: more detail on major failure mechanisms Logic –Re-evaluate scaling (assumptions, requirements and simplified models) for high-performance and low-power –Re-evaluate gate leakage specifications, esp. high-performance –Add embedded SRAM roadmap

10. 24 July 2002 Work In Progress – Not for Publication Model-Based MOSFET Scaling Approach: 2001 ITRS Simple models capture essential MOSFET physics embedded in a spreadsheet –Initial choice of scaled MOSFET parameters is made –Using spreadsheet, MOSFET parameters are iteratively varied to meet ITRS targets Types of Logic –High Performance: target is historical 17%/year performance increase –Low Power: target is specific, low level of leakage current Low Standby Power (LSTP): very low power (i.e., cellphone) Low Operating Power (LOP): low power, rel. high performance (i.e., notebook computer)

11. 24 July 2002 Work In Progress – Not for Publication Scaling of Leakage Current and 1/ I sd,leak, High Perf. I sd,leak, Low Power (LSTP) 1/, Low Power (LSTP) 1/, High Perf.

12. 24 July 2002 Work In Progress – Not for Publication MOSFET Scaling Results High-performance logic –Average 17%/yr improvement in 1/ is attained –I sd,leak is very high, particularly for 2007 and beyond chip static power dissipation scaling is an issue Assumption: I gate I sd,leak uncomfortably large I gate Low-power logic (particularly LSTP) –Very low I sd,leak target is met I gate I sd,leak I gate is very low: will require high-k by around 2005 –1/ scales considerably slower than for high- performance

13. 24 July 2002 Work In Progress – Not for Publication LSTP: Maximum Gate Leakage Specs. and Simulations: Need for High K 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 20012003200520072009201120132015 Year J g (A/cm 2 ) 0 0.5 1 1.5 2 2.5 3 EOT (nm) Simulated J g, oxynitride Specified J g (<I sd,leak /L g per 2001 ITRS) EOT Beyond this point, oxynitride too leaky; high K needed LSTP is projected to drive the implementation of high-k gate dielectric in ~2005.

14. 24 July 2002 Work In Progress – Not for Publication Key Cross-TWG Issues: Logic With FEP –Parasitic R s,d modeling: PMOS and NMOS –Gate leakage current requirements, esp. for high-performance logic –L eff : process control requirements –SOI requirements –Model for impact of poly depletion –Begin to evaluate process and material requirements for non- classical CMOS With Design –Review model-based scaling and assumptions –Deal with static power dissipation issues for high-performance logic Use of multi-V t, multi-T ox Circuit design, architecture power conditioning techniques Dynamic or electrically alterable V t

15. 24 July 2002 Work In Progress – Not for Publication PIDS Summary 2002: minor updates and corrections 2003: considerable re-evaluation, significant changes are contemplated Emerging Research Devices: Jim Hutchby will discuss this

16. 24 July 2002 Work In Progress – Not for Publication July 2002 ITRS Meeting PIDS ITWG Emerging Research Devices Working Group Jim Hutchby San Francisco, CA July 24, 2002

17. 24 July 2002 Work In Progress – Not for Publication PIDS ITWG Research Devices Working Group Participants u George BourinaoffIntel/SRC u Joop BruinesPhilips u Joe BrewerU. Florida u Jim ChungCompaq u Peng FangAMAT u Steve HilleniusAgere u Toshiro HiramotoTokyo U. u Jim HutchbySRC u Dae Gwan KangHynix u Mike Forshaw (UC London) u Tsu-Jae King (UC Berkeley) u Herb BennettNIST u Makoto Yoshimi Toshiba u Kentaro Shibahara Hiroshima U. u Kristin De MeyerIMEC u Tak Ning IBM u Byong Gook ParkSeoul N. U. u Luan TranMicron u Bin ZhaoConexant u Victor ZhirnovSRC/NCSU u Ramon CompanoEurope Com u Simon Deleonibus (LETI) u Thomas Skotnicki (ST Me) u Yuegang ZhangIntel

18. 24 July 2002 Work In Progress – Not for Publication PIDS Emerging Research Devices Working Group Directions for 2003 Technology Transfers uNon classical CMOS (PIDS and FEP) –FDSOI (not including Ultra-Thin Body SOI with t si < 10 nm) –Strained Si for enhanced channel mobility uMemory (PIDS and FEP) –MRAM –Phase Change Memory uArchitecture (Assembly and Packaging) –3D Integration using mechanical wafer attachment techniques Technology Additions uCapacitor-less DRAM cell uQuantum memories uSpintronics uSilicon nanowires

19. 24 July 2002 Work In Progress – Not for Publication PIDS Emerging Research Devices Working Group Directions for 2003 uAdd another node (15-nm node) to the 2003 Roadmap for CMOS? –Silicon MOSFETs will operate for channel lengths down to 5 nm. –IRC will determine node timing. uElevate Mixed Signal as a new technology driver (joining DRAM and MPU/ASIC) in the 2003 ITRS to support wireless applications. Potential Solutions new to the ITRS include: –Compound semiconductor technologies (GaAs and InP) –MEMS Technologies uCritically evaluate new Information Processing Technologies, based on application needs and technical criteria.