1. Summer Public Conference ORTC 2010 Update Messages
A. Allan, 07/14/10, Rev 8
Work in Progress – Do Not Publish!

2. Summer Update to the 4/3 Italy 2009 ITRS ORTC
ORTC Model Proposals to TWGs for TWG Interdependency Preparation for other ORTC section features:
“Beyond CMOS” timing unchanged in 2010 for ERD/ERM early research and transfer to PIDS; however need for continued discussion about transfer of III/V Gate Material technology in 2011 Renewal
Logic “Equivalent Scaling” Roadmap Timing Update underway, and ongoing discussion of alignment of “node” and dimensional Trends for 2011 Renewal
New “More than Moore” (MtM) white paper draft review and discussion underway for 2011 ITRS Renewal impact and added to the ITRS website at
MPU contacted M1
Unchanged for 2010 [validated by FEP data]
2-year cycle trend through 2013
Cross-over DRAM M1 2010/45nm
Smaller 60f2 SRAM 6t cell Design Factor
Smaller 175f2 Logic Gate 4t Design Factor
Proposal from Taiwan [2011 Renewal]: Design TWG evaluate 1-year pull-in of M1
DRAM contacted M1
Unchanged for 2010: Dimensional M1 half-pitch trends remain unchanged from 2007/08/09 ITRS; new 4f2 Design factor begins 2011
Proposal [2011 Renewal]: 1-year pull-in of M1 and bits/chip trends; 4f2 push out
Flash Un-contacted Poly
Unchanged for 2010: 2yr cycle trend through 2010/32nm; then 3yr cycle and also added “equivalent scaling” bit design:
Inserted 3bits/cell MLC ; and delayed 4bits/cell (2 companies in production) until 2012
Proposal [2011 Renewal]: 1-year pull-in of Poly; however 3bits/cell extended to 2018; 4bits/cell delay to 2019
Work in Progress – Do Not Publish!

3. Italy 4/9 Update to the 12/16 Taiwan 2009 ITRS ORTC (cont.)
5) Unchanged for 2010 Tables: MPU GLpr – ’08-’09 2-yr flat; Low operating and standby line items track changes
Unchanged for 2010 Tables: MPU GLph – ’08-’09 2-yr flat with equiv. scaling process tradeoffs; Low operating and standby line items track changes
Performance targets (speed, power) on track with tradeoffs
7) Unchanged for 2010 Tables: MPU Functions/Chip and Chip Size Models
Utilized Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and updated cell design factors
ORTC line item OverHead (OH) area model, includes non-active area
ORTC model impact from Taiwan proposal will be evaluated for 2011 Renewal
DRAM Bits/Chip and Chip Size Model Unchanged for 2010 Tables - 3-year generation “Moore’s Law” doubling cycle;
smaller Chip Sizes (<60mm2) with 4f2 design factor included
ORTC model impact updating from PIDS/FEP Survey proposals will be evaluated for 2011 Renewal
Flash Bits/Chip and Chip Size Model Unchanged for 2010 Tables
2-year generation “Moore’s Law” doubling cycle;
growing Chip Sizes after return to 3-year technology cycle
ORTC model impact updating from PIDS/FEP Survey proposals will be evaluated for 2011 Renewal]
IRC 450mm Position: Pilot lines/2012; Production/ Unchanged for 2010; also Unchanged: “double S-curve” graphic in 2009 Executive Summary
450mm Program status and Long-Range IEM v12 Demand Update Scenario was presented by ISMI to IRC for 2011 ITRS Renewal preparation
ISMI believes the 450mm program is presently on track to meet ITRS Timing
Work in Progress – Do Not Publish!

4. 2009 Definition of the Half Pitch – unchanged
[No single-product “node” designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables]
Source: ITRS - Exec. Summary Fig 1
Poly
Pitch
Typical flash
Un-contacted Poly
FLASH Poly Silicon ½ Pitch
= Flash Poly Pitch/2
8-16 Lines
Metal
Typical DRAM/MPU/ASIC
Metal Bit Line
DRAM ½ Pitch
= DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch
= MPU/ASIC M1 Pitch/2
Work in Progress – Do Not Publish!

5. Production Ramp-up Model and Technology Cycle Timing
2009 – Unchanged
Production Ramp-up Model and Technology/Cycle Timing
Months
-24
Alpha
Tool 12 24
-12
Development
Production
Beta
First
Conf.
Papers
First Two Companies
Reaching Production 2 20
200 2K
20K
200K
Additional
Lead-time:
ERD/ERM
Research and
PIDS Transfer
Volume (Wafers/Month)
Production Ramp-up Model and Technology Cycle Timing
*Examples: 25Kwspm ~=
280mm2
140mm2
100mm2
70mm2
Source: ITRS - Exec. Summary Fig 2a
Work in Progress – Do Not Publish!

6. 2007 ITRS Executive Summary Fig 4
2009 WAS
Continuing SoC and SiP: Higher Value Systems
Traditional
ORTC Models
[Geometrical & Equivalent scaling]
Scaling (More Moore)
Functional Diversification (More than Moore) HV
Power
Passives
2007 ITRS Executive Summary Fig 4
New work
In 2009
New in 2009:
Research and PIDS transfer timing clarified
Work underway to identify next storage element
Online in 2008:
SIP “White Paper”
More than Moore
“White Paper”
More Commentary
In ITWG Chapters
Survey updates
to ORTC Models
Equivalent Scaling
Roadmap Timing
Synchronized with
PIDS and FEP
Source: ITRS Executive Summary Fig 1
Work in Progress – Do Not Publish!

7. 2010 Update/2011 Renewal MtM Graphic Proposal from Europe IRC
2010 MtM White Paper
Update
Moore’s Law & More
More than Moore: Diversification
More Moore: Miniaturization
Combining SoC and SiP: Higher Value Systems
Baseline CMOS: CPU, Memory, Logic
Biochips
Sensors
Actuators HV
Power
Analog/RF
Passives
130nm
90nm
65nm
45nm
32nm
22nm
16 nm . V
Information
Processing
Digital content
System-on-chip
(SoC)
Beyond CMOS
Interacting with people and environment
Non-digital content
System-in-package
(SiP)
[Note: iNEMI Roadmap work will
Propose additional modifications and
Cross-roadmap alignment work
To the IRC at the July USA ITRS
Meetings]
Work in Progress – Do Not Publish!

8. + III/V High µ Alternative Channel Mat’ls
Equivalent Scaling Process Technologies Timing
WAS 2009
Current figure 8c in ITRS executive summary (page 69)
[Orig. Source: ITRS, European Nanoelectronics Initiative Advisory Council] (ENIAC)
Source: ITRS - Exec. Summary, Fig 8c, Equivalent Scaling Process Technologies Timing
PDSOI
FDSOI
bulk
stressors
+ high µ SiGe materials
MuGFET
MuCFET
Electrostatic
control
SiON
poly
high k
metal
Gate
stack
+ III/V High µ Alternative Channel Mat’ls
Channel
material
high k [II, etc]
Work in Progress – Do Not Publish!

9. Work in Progress – Do Not Publish!
Equivalent Scaling Process Technologies Timing
Final Proposal for 2011 work
Proposed figure 8c in ITRS executive summary
Metal
High k
Metal
High k
2nd generation
Metal
High k
nth generation
Gate-stack material
Si + Stress S D
High-µ
material ? S D
Channel
material
Bulk
Multi-gate
(on bulk or SOI)
Structure (electrostatic control)
PDSOI
FDSOI
2009
2012
2015
2018
2021
See also PIDS, FEP, ERD, and ERM chapters’ text and tables for additional detail)
= Additional timing movement
considerations for 2011 ITRS work
Work in Progress – Do Not Publish!

10. Work in Progress – Do Not Publish!
ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing
[Example: III-V MOSFET High-mobility Channel Replacement Materials]
Source: ITRS - Executive Summary Fig 2b
Months
Alpha
Tool
Development
Production
Beta
Product
Volume (Wafers/Month) 2 20
200 2K
20K
200K
Research
-72 24
-48
-24
-96
Transfer to PIDS/FEP
(96-72mo
Leadtime)
First
Tech. Conf.
Device Papers
Up to ~12yrs
Prior to Product
2019
2017
2015
2013
2011
2021
III/V Hi-m gate
Example:
1st 2 Co’s
Reach
Circuits Papers
Up to ~ 5yrs
2009
Unchanged
Work in Progress – Do Not Publish! 10

11. 450mm Production Ramp-up Model
Volume
Years
Alpha
Tool
Beta
Tools for
Pilot line
32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011
Consortium Pilot Line
Manufacturing
22nm (extendable to 16nm) M1 half-pitch capable tools
Development
Production
450mm 32nm M1 half-pitch
Pilot Line Ramp
2010
2011
2012
2013
2014
2015
2016
450mm Production Ramp-up Model
[ 2009  Figure 2c  A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Source: ITRS - Executive Summary Fig 2c
2009 Unchanged
Work in Progress – Do Not Publish!

12. IRC Graphic update Proposal Considerations
Also 450mm “Dual S-Curve” and possible alignment with “Node vs. Technology Trends”
Work in Progress – Do Not Publish!

13. 450mm Production Ramp-up Model
[ 2009  ITRS Figure 2c  A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Versus “Node”/actual contacted M1 and un-contacted Poly Half-Pitch alignment
2009 WAS
2009 ITWG Table Timing:
68nm
45nm
32nm
22nm
16nm
2009 IS ITRS DRAM M1 :
2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm nm nm
MPU/hpASIC “Node”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”
2009 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm
2009 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm
11nm
2009 IS ITRS Flash Poly :
54nm
New for 2009
Volume
Years
Alpha
Tool
Beta
Tools for
Pilot line
32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011
Consortium Pilot Line
Manufacturing
22nm (extendable to 16nm) M1 half-pitch capable tools
Development
Production
450mm 32nm M1 half-pitch
Pilot Line Ramp
2010
2011
2012
2013
2014
2015
2016
450mm Production Ramp-up Model
[ 2009  Figure 2c  A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Source: ITRS - Executive Summary Fig 2c
Work in Progress – Do Not Publish! 13

14. Work in Progress – Do Not Publish!
2009 WAS
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
>0.7mm mm mm mm mm mm
<0.08mm mm
Feature Size (Half Pitch) (mm)
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual
= 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target
= 2009 ITRS Flash Uncontacted Poly Half Pitch Target
= 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
3-Year Cycle
2008/09 ITRS: 2.5-Year Ave Cycle for DRAM
3-Year Cycle
After 2010 for
Flash; after 2013
For MPU
2-Year DRAM Cycle
3-Year DRAM Cycle ; 2-year Cycle Flash and MPU
Year
2010
2013
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009. 
The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range
of the feature size (y-axis). Data are based upon capacity if fully utilized.
Source: ITRS - Executive Summary Fig 3
Work in Progress – Do Not Publish!

15. 4Q09 SICAS Update Proposal Work in Progress – Do Not Publish!
From Furukawa-san/Japan
To IRC 3/28/10 (modified by AA)
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
>0.7mm mm mm mm mm mm
<0.08mm mm
<0.06mm
Feature Size (Half Pitch) (mm)
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual
= 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target
= 2009 ITRS Flash Un-contacted Poly Half Pitch Target
= 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
3-Year Cycle
2008/09 ITRS: 2.5-Year Ave Cycle for DRAM
3-Year Cycle
After 2010 for
Flash; after 2013
For MPU
2-Year DRAM Cycle
3-Year DRAM Cycle ; 2-year Cycle Flash and MPU
Year
Year
2010
2013
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009. 
The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range
of the feature size (y-axis). Data are based upon capacity if fully utilized.
Source: ITRS - Executive Summary Fig 3
Work in Progress – Do Not Publish!