Microelectronic Device Fabrication n-well p-channel transistor p-well n-channel transistor p+ substrate Transistor Layers Prof. Dr. Ir. Djoko Hartanto, M.Sc Arief Udhiarto, S.T,M.T Electrical Engineering Department University of Indonesia

Terms and Concepts to be Covered in this Lesson silicon substrate monocrystalline polycrystalline epitaxial silicon growth polysilicon silicon dioxide oxide silicon nitride metal dopant doping concentration diffusion field effect transistor source, drain, gate 3 3 3 3 3 3 3 3 3

Terms and Concepts to be Covered in this Lesson MOS NMOS technology n-channel PMOS technology p-channel CMOS technology p-well n-well photoresist photomask exposure diffusion thin films photolithography etch ion implant polish, CMP planarization strips and cleans test and sort 4 4 4 4 4 4 4 4 4

Variations in Dopant Concentrations Concentration P-type N-type lightly doped p- n- very lightly doped p-- n-- heavily doped p+ n+ very heavily doped p++ n++ 5 5 5 5 5 5 5 5

Processing Overview Processing Overview Steps to Chip IC Fabrication Material Preparation Convert silicon dioxide to semiconductor-grade silicon Crystal Growth and Wafer Preparation Convert polysilicon to silicon wafer Crystal growing Slice cutting and polishing Photomask manufacturing

Procesing Overview Processing Overview Wafer Fabrication Cleaning of surfaces Growth of epitaxial layer Thermal oxidation of silicon Patterning of the various layers (lithography) Diffusion of impurities into silicon Ion implantation of impurities

Wafer Fabrication Processing Overview Chemical vapor deposition of polycristalline silicon Etching of silicon and GaAs Deposition of insulating layers (silicon oxide or nitride) Etching of insulating layers (silicon oxide or nitride) Depositon of conductive layers (metal, polysilicon, other) Alloying (sintering) to form metal-silicon electrical contact

Wafer Fabrication Processing Overview Backgrinding (thinning of wafer by grinding) Multiprobing (DC electrical testing of each IC on wafer)

4. Packaging Processing Overview Cutting or breaking of wafers into individual chips Packaging of individual chips Full AC dan DC electrical testing of packaged ICs

Fabrication process of a simple metal oxide semiconductor (MOS) transistor silicon substrate source drain gate oxide top nitride metal connection to source metal connection to gate metal connection to drain polysilicon gate doped silicon field oxide gate oxide 6 6 6 6 6 6 6 6 6

The manufacture of a single MOS transistor begins with a silicon substrate. 7 7 7 7 7 7 7 7 7

A layer of silicon dioxide (field oxide) provides isolation between devices manufactured on the same substrate. silicon substrate oxide field oxide 8 8 8 3 8 8 8 8 8 8

Photoresist provides the means for transferring the image of a mask onto the top surface of the wafer. photoresist oxide silicon substrate 9 9 4 9 9 9 9 9 9 9

Ultraviolet light exposes photoresist through windows in a photomask. Chrome plated glass mask Shadow on photoresist Exposed area of photoresist photoresist oxide silicon substrate 10 10 5 10 10 10 10 10 10 10

Ultraviolet light exposes photoresist through windows in a photomask. Chrome plated glass mask Shadow on photoresist Exposed area of photoresist photoresist oxide silicon substrate

Exposed photoresist becomes soluble and can be easily removed by the develop chemical. Unexposed area of photoresist silicon substrate Exposed area of photoresist oxide photoresist 11 11 11 6 11 11 11 11 11 11

Unexposed photoresist remains on surface of oxide to serve as a temporary protective mask for areas of the oxide that are not to be etched. Shadow on photoresist silicon substrate oxide photoresist 12 12 7 12 12 12 12 12 12 12

Areas of oxide protected by photoresist remain on the silicon substrate while exposed oxide is removed by the etching process. silicon substrate oxide photoresist 13 13 13 8 13 13 13 13 13 13

The photoresist is stripped off -- revealing the pattern of the field oxide. silicon substrate oxide field oxide 14 14 14 14 14 14 14 14 14

A thin layer of oxide is grown on the silicon and will later serve as the gate oxide insulator for the transistor being constructed. silicon substrate oxide gate oxide thin oxide layer 15 15 15 9 15 15 15 15 15 15

The gate insulator area is defined by patterning the gate oxide with a masking and etching process. silicon substrate oxide gate oxide 16 16 16 10 16 16 16 16 16 16

Polysilicon is deposited and will serve as the building material for the gate of the transistor. silicon substrate oxide gate oxide polysilicon 17 17 17 11 17 17 17 17 17 17

The shape of the gate is defined by a masking and etching step. silicon substrate oxide gate ultra-thin gate oxide polysilicon 18 18 18 12 18 18 18 18 18 18

Dopant ions are selectively implanted through windows in the photoresist mask. silicon substrate oxide gate photoresist Scanning direction of ion beam implanted ions in active region of transistors Implanted ions in photoresist to be removed during resist strip. source drain ion beam 19 19 19 19 19 19 19 19 19

The source and drain regions of the transistor are made conductive by implanting dopant atoms into selected areas of the substrate. silicon substrate oxide gate source drain doped silicon 20 20 20 13 20 20 20 20 20 20

A layer of silicon nitride is deposited on top of the completed transistor to protect it from the environment. silicon substrate source drain gate top nitride 21 21 21 14 21 21 21 21 21 21

Holes are etched into selected parts of the top nitride where metal contacts will be formed. silicon substrate source drain gate contact holes 22 22 22 15 22 22 22 22 22 22

Metal is deposited and selectively etched to provide electrical contacts to the three active parts of the transistor. silicon substrate source drain gate oxide metal contacts 23 23 23 23 23 23 23 23 23

Completed structure of a simple MOS transistor silicon substrate source drain gate oxide top nitride metal connection to source metal connection to gate metal connection to drain polysilicon gate doped silicon field oxide gate oxide 24 24 24 24 24 24 24 24 24

Manufacturing Areas in Wafer Fab Wafer Fabrication (front-end) Thin Films Polish Bare silicon wafer Diffusion Photo Etch Completed product Implant Test/Sort 25 25 25 25 25 25 25 25 25

Common Terms in Wafer Fab Diffusion high temperature processes atmospheric - low vacuum pressures oxidation, anneal, alloy, deposition, diffusion Photolithography patterning process (masking) photoresist coating exposure to UV light develop 26 26 26 26 26 26 26 26 26

Common Terms in Wafer Fab Etch selective removal of specific materials permanent patterning of wafer low vacuum - high vacuum pressure RF power, plasma etching Ion Implant selective doping of specific areas of wafer through windows in photoresist or oxide high voltage, high vacuum, ion acceleration 27 27 27 27 27 27 27 27 27

Common Terms in Wafer Fab Thin Films moderate temperatures low vacuum - high vacuum pressures dielectric films, metals, anneal Polish chemical mechanical polish (CMP) planarization of wafer surface 28 28 28 28 28 28 28 28 28

Common Terms in Wafer Fab Strips & Cleans dry, plasma resist strip wet, chemical cleans using acid solutions and solvents Test/Sort automated testing of each die on wafer discriminate good from bad determines a fab’s yield ship to assembly & packaging 29 29 29 29 29 29 29 29 29

Typical Wafer Flow in CMOS Fab Thin Films Photo Implant Diffusion Etch Test/Sort Polish 30

CMOS Inverter Technology VDD VSS Vout Vin s d g Schematic Diagram VDD VSS Vout Vin g s d Top view of Transistor n-channel transistor p-channel p-well n+ p+ n-substrate source drain field oxide gate oxide metal polysilicon gate contact Cross-section of Transistor