1. Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist deposition yUV light exposure through Mask yChemical etching for removal of xPhotoresist xoxide layer zPattern formed Process used to transfer patterns to each layer of IC

2. Lecture #52 NMOS Transistor Polysilicon Gate Field Oxide (Thick Oxide) Gate Oxide (Thin Oxide)

3. Lecture #53 Patterning Silicon Si - Substarate Silicon Di-oxide

4. Lecture #54 Process steps for Patterning Light Sensitive organic polymer Grow Crystal Saw Silicon Wafer Oxide Layer S i O 2  1  m Silicon Wafer Oxide Layer Photoresist Bare silicon Wafer Grow Oxide Layer Spin coating with Photoresist –1mm Thermal Oxidation Acid-resistant Soluble once exposed to UV Light 4-12” dia <1mm

5. Lecture #55 Pattern formed on a glass plate (Mask)  Transparent & Opaque regions Positive Photoresist  Non exposed regions hardened  higher resolution (hardened) Silicon Wafer Oxide Layer Exposed soluble Expose to Ultraviolet Light

6. Lecture #56 Etching continued to remove SiO 2 Pattern formed Silicon Wafer Oxide Layer Silicon Wafer Soluble photoresist is chemically removed (etching) using HF acid High-temp. plasma removes hardened photoresist

7. Lecture #57 Patterned Silicon Si - Substarate

8. Lecture #58 (l)

9. Lecture #59 n-well CMOS Process

10. Lecture #510 Grow CrystalSaw The CMOS Process – Photolithography (1)

11. Lecture #511 The CMOS Process – Photolithography (2)

12. Lecture #512 Impurity Implantation Mask 1: N-well Diffusion

13. Lecture #513 Mask 2: Define Active Regions

14. Lecture #514 Mask 3: Polysilicon Gate

15. Lecture #515 Mask 4: n+ Diffusion

16. Lecture #516 Mask 5: p+ Diffusion

17. Lecture #517 Mask 6: Contact Holes

18. Lecture #518 Mask 7: Metallization

19. Lecture #519 Cross Section of a CMOS Inverter

20. Lecture #520 P- Substrate N -Channel P -Channel L W L IN GND OUT Vdd S G D D G S N -Well

21. Lecture #521 Layout of CMOS ICs Translating the circuit schematic into a set of patterned layers in a silicon substrate Layout drawings are used to generate the masks needed for fabrication Every layer is described by geometrical objects of specified shape and size obeying certain rules (Design Rules). Each layer is described by a distinct color

22. Lecture #522 Why do we need design rules? zMasks are tooling for manufacturing. zManufacturing processes have inherent limitations in accuracy. zDesign rules specify geometry of masks which will provide reasonable yields. zDesign rules are determined by experience zDesign rule violation may result in a non- functional circuit

23. Lecture #523 Manufacturing Problems zPhotoresist shrinkage, tearing. zVariations in material deposition. zVariations in temperature. zVariations in oxide thickness. zImpurities. zVariations between lots. zVariations across a wafer.

24. Lecture #524 Transistor Problems zVariations in threshold voltage: yoxide thickness; yion implantation; ypoly variations. zChanges in source/drain diffusion overlap. zVariations in substrate.

25. Lecture #525 Wiring problems zDiffusion: changes in doping -> variations in resistance, capacitance. zPoly, metal: variations in height, width -> variations in resistance, capacitance. zShorts and opens:

26. Lecture #526 Oxide problems zVariations in height. zLack of planarity -> step coverage. metal 1 metal 2

27. Lecture #527 Via Problems zVia may not be cut all the way through. zUndersized via has too much resistance. zVia may be too large and create short.