ETE 204 - Digital Electronics Latches and Flip-Flops [Lecture:12] Instructor: Sajib Roy Lecturer, ETE, ULAB.

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ETE Digital Electronics Latches and Flip-Flops [Lecture:12] Instructor: Sajib Roy Lecturer, ETE, ULAB

Brief introduction to Sequential Logic Circuits Summer 2012ETE Digital Electronics2

Sequential Logic Circuits ● The output of a sequential logic circuit is dependent not only on the present inputs, but also on the past sequence of the inputs. ● A sequential logic circuit must “remember” the past history of the inputs. ● It does this using basic memory elements. - Latches - Flip-Flops 3Summer 2012ETE Digital Electronics

Sequential Logic Circuits inputs Combinational Logic Circuit outputs Memory 4Summer 2012ETE Digital Electronics

Basic Memory Elements 5Summer 2012ETE Digital Electronics

Basic Memory Elements ● Latch - Clock input is level sensitive. - Output can change multiple times during a clock cycle. - Output changes while clock is active. ● Flip-Flop - Clock input is edge sensitive. - Output can change only once during a clock cycle. - Output changes on clock transition. 6Summer 2012ETE Digital Electronics

Basic Memory Elements Both latches and flip-flops use feedback to achieve “memory”. 7Summer 2012ETE Digital Electronics

Feedback Circuit with 2 Stable States What is the problem with this circuit? 8Summer 2012ETE Digital Electronics

Latches 9Summer 2012ETE Digital Electronics

Set-Reset (SR) Latch ● A Set-Reset Latch has two inputs - Set (S) input - Reset (R) input ● It can be constructed from two cross-coupled NOR gates or two cross-coupled NAND gates. ● It has three modes of operation - Set:Latch output set to 1 (Q + = 1) – Reset: Latch output reset to 0 (Q + = 0) - Store: Latch output does not change (Q + = Q) 10Summer 2012ETE Digital Electronics

SR Latch: using NOR gates ABNOR 0XX' 1X0 FeedbackNOR gates 11Summer 2012ETE Digital Electronics

SR Latch: Set (S = 1, R = 0) ABNOR 0XX' 1X0 1 0 P = Q' Summer 2012ETE Digital Electronics

SR Latch: Reset (S = 0, R = 1) ABNOR 0XX' 1X0 0 1 P = Q' Summer 2012ETE Digital Electronics

SR Latch: Store (S = 0, R = 0) Initial Condition: P = 0, Q = 1 ABNOR 0XX' 1X0 0 0 P = Q' Summer 2012ETE Digital Electronics

SR Latch: Store (S = 0, R = 0) Initial Condition: P = 1, Q = 0 ABNOR 0XX' 1X0 0 1 P = Q' Summer 2012ETE Digital Electronics

SR Latch: Behavior PresentNext value SRQQ+Q If S = 1 (Set), Q + = 1 If R = 1 (Reset), Q + = If S = R = 0, Q + = Q (no change) not S = R = 1 is not allowed. 111allowed 16Summer 2012ETE Digital Electronics

SR Latch: Improper Operation P ≠ Q ′ 17Summer 2012ETE Digital Electronics

SR Latch: Symbol always complementary Q' Q SQSQ SR Latch RQ' 18Summer 2012ETE Digital Electronics

SR Latch: Timing Diagram storesetstorereset Q' Q  = propagation delay of the latch 19Summer 2012ETE Digital Electronics

SR Latch: Characteristic Equation Q = present state Q + = next state Characteristic Equation: Q + = S + R'.Q(S.R = 0) 20Summer 2012ETE Digital Electronics

SR Latch: using NAND gates ABNAND 0X1 1XX' S'R'Q Q+Q not 001allowed 21Summer 2012ETE Digital Electronics

Gated D Latch ● A Gated D Latch has two inputs - Gate (G) input - Data (D) input ● It can be constructed from an SR Latch and additional logic gates. ● It has the following behavior - G = 1: D is passed to Q (Q + = D) - G = 0: Q remains unchanged (Q + = Q) ● Also referred to as a transparent latch. 22Summer 2012ETE Digital Electronics

Gated D Latch: Circuit and Timing NOR gates 23 Summer 2012ETE Digital Electronics

Gated D Latch: Symbol and Truth Table No invalid inputs! 24Summer 2012ETE Digital Electronics

Gated D Latch: Characteristic Equation Characteristic Equation: Q + = G'.Q + G.D Spring 2011ECE 30 - Digital Electronics25Summer 2012ETE Digital Electronics

Gated D Latch: using NAND gates S' R' NAND gates 26Summer 2012ETE Digital Electronics

Flip-Flops 27Summer 2012ETE Digital Electronics

D Flip-Flop ● A D Flip-Flop has two inputs - Clock (Ck) --- denoted by the small arrowhead - Data (D) ● The output of the D Flip-Flop changes in response to the clock input only. - not in response to a change in the D input ● The D Flip-Flop is edge-triggered not level-sensitive - Positive (or rising) edge-triggered: 0 → 1 – Negative (or falling) edge-triggered: 1 → 0 28Summer 2012ETE Digital Electronics

D Flip-Flop Characteristic Equation: Q + = D 29 Summer 2012ETE Digital Electronics

D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on? 30Summer 2012ETE Digital Electronics

D Flip-Flop (master-slave) Gated D Latches Enabled on opposite levels of the clock 31Summer 2012ETE Digital Electronics

D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on? 32Summer 2012ETE Digital Electronics

D Flip-Flop: Setup and Hold Times Setup time Hold time Propagation delay 33Summer 2012ETE Digital Electronics

D Flip-Flop: Minimum Clock Period 34 Summer 2012ETE Digital Electronics

Questions? 35Summer 2012ETE Digital Electronics