1. Digital Logic Design Brief introduction to Sequential Circuits and Latches

2. ECE 301 - Digital Electronics2 Sequential Logic Circuits

3. ECE 301 - Digital Electronics3 Sequential Logic Circuits Combinational Logic Circuits  Output is a function of the inputs only.  Do not have “history” Sequential Logic Circuits  Output is a function of the inputs and the present state.  Have “history”  Maintain state information  Require memory elements

4. ECE 301 - Digital Electronics4 Sequential Logic Circuits

5. ECE 301 - Digital Electronics5 Basic Memory Elements

6. ECE 301 - Digital Electronics6 Basic Memory Elements Latch  Clock input is level sensitive.  Output can change multiple times during a clock cycle.  Output changes while clock is active. Flip Flop  Clock input is edge sensitive.  Output can change only once during a clock cycle.  Output changes on clock transition.

7. ECE 301 - Digital Electronics7 Basic Memory Elements Both latches and flip flops use feedback to achieve “memory”.

8. ECE 301 - Digital Electronics8 SR Latch (NOR gate implementation)

9. ECE 301 - Digital Electronics9 SR Latch QaQa QbQb QbQb QaQa

10. ECE 301 - Digital Electronics10 The undefined state of the SR Latch (Qa = Qb = 0) SR Latch

11. ECE 301 - Digital Electronics11 SR Latch (NAND gate implementation)

12. ECE 301 - Digital Electronics12 SR Latch

13. ECE 301 - Digital Electronics13 Gated SR Latch (NAND Gate Implementation)

14. ECE 301 - Digital Electronics14 Gated SR Latch S' R'

15. ECE 301 - Digital Electronics15 Gated SR Latch: State Equation State Equation: Q + = S + R'.Q  Q is the present (or current) state.  Q + is the next state. After the transition of the output Q.  The next state is a function of the inputs and the present state. Inputs: S and R Present State: Q  Note: Q is also denoted as Q(t)  and Q + is also denoted as Q(t+1).

16. ECE 301 - Digital Electronics16 Gated D Latch

17. ECE 301 - Digital Electronics17 Gated D Latch S' R' S R

18. ECE 301 - Digital Electronics18 Gated D Latch: Clk = 0 Clk = 0 Clk = 0 → S' = R' = 1 S' = R' = 1 → Q + = Q  Next state = present state Latch stores the value of Q

19. ECE 301 - Digital Electronics19 Gated D Latch: Clk = 1 Clk = 1 Clk = 1 → S' = D', R' = D S' = D', R' = D → Q + = D  Next state = input Output (Q) follows the input (D)

20. ECE 301 - Digital Electronics20 Gated D Latch State Equation: Q + = D  Q + is the next state  D is the input Eliminates the unstable case  S' = R' = 0 cannot occur. S' = R' = 0 is the same as S = R = 1.  The values of S' and R' are always complementary when the clock is high (active).