1. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust © 2008 Pearson Education Chapter 7

2. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed In this lecture we cover: 7-1 Latches 7-2 Edge Triggered Flip-Flops 7-3 Flip-Flop Operating Characteristics 7-4 Flip-Flop Applications

3. Chapter Objectives  In this chapter you will learn about:  Logic circuits that can store information  Flip-flops, which store a single bit  Registers, which store multiple bits  Shift registers, which shift the contents of a register  Counters of various types  VHDL constructs used to implement storage elements  Design of small subsystems  Timing considerations

4. Memory element Alarm Sensor Reset Set OnOff  Motivation: Control of an Alarm System  Alarm turned on when On/Off = 1  Alarm turned off when On/Off = 0  Once triggered, alarm stays on until manually reset  The circuit requires a memory element

5. The Basic Latch  Basic latch is a feedback connection of two NOR gates or two NAND gates  It can store one bit of information  It can be set to 1 using the S input and reset to 0 using the R input.

6. AB A Simple Memory Element  A feedback loop with even number of inverters  If A = 0, B = 1 or when A = 1, B = 0  This circuit is not useful due to the lack of a mechanism for changing its state

7. Reset SetQ A Memory Element with NOR Gates

8. The Gated Latch  Gated latch is a basic latch that includes input gating and a control signal  The latch retains its existing state when the control input is equal to 0  Its state may be changed when the control signal is equal to 1. In our discussion we referred to the control input as the clock  We consider two types of gated latches:  Gated SR latch uses the S and R inputs to set the latch to 1 or reset it to 0, respectively.  Gated D latch uses the D input to force the latch into a state that has the same logic value as the D input.

9. Gated S/R Latch

10. Gated D Latch

11. t su t h Clk D Q Setup and Hold Times  Setup Time t su  The minimum time that the input signal must be stable prior to the edge of the clock signal.  Hold Time t h  The minimum time that the input signal must be stable after the edge of the clock signal.

12. Flip-Flops  A flip-flop is a storage element based on the gated latch principle  It can have its output state changed only on the edge of the controlling clock signal

13. Flip-Flops  We consider two types:  Edge-triggered flip-flop is affected only by the input values present when the active edge of the clock occurs  Master-slave flip-flop is built with two gated latches  The master stage is active during half of the clock cycle, and the slave stage is active during the other half.  The output value of the flip-flop changes on the edge of the clock that activates the transfer into the slave stage.

14. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s D Q m QQ s = D Q Q (a) Circuit (b) Timing diagram (c) Graphical symbol Clk Master-Slave D Flip-Flop

15. D Q Q Graphical symbol Clock A Positive-Edge-Triggered D Flip-Flop

16. Comparison of Level-Sensitive and Edge- Triggered D Storage Elements

17. D Q Q Clear Preset Master-Slave D Flip-Flop with Clear and Preset

18. T Flip-Flop

19. JK Flip-Flop

20. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Next lecture covers: 9-1 Basic Shift Register Operation 9-2 Serial -In / Serial--Out Shift Registers 9-3 Serial -In / Parallel--Out Shift Registers 9-4 Parallel -In / Serial--Out Shift Registers 9-5 Parallel -In / Parallel--Out Shift Registers