1. Sequential logic circuits

2. Sequential logic circuits
Outline
Sequential Circuit Models
Asynchronous
Synchronous
Latches
Flip-Flops
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Sequential logic circuits

3. Sequential logic circuits
The main characteristic of combinational logic circuits is that their output values depend on their present input values.
Sequential logic circuits differ from combinational logic circuits because they contain memory elements so that their output values depend on both present and past input values
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Sequential logic circuits

4. Sequential logic circuits
Sequential circuits can be Asynchronous or synchronous.
Asynchronous sequential circuits change their states and output values whenever a change in input values occurs.
Synchronous sequential circuits change their states and output values at fixed points of time, i.e. clock signals.
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Sequential logic circuits

5. Sequential Circuit Models
Universal model
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Sequential logic circuits

6. Sequential logic circuits
Combinational circuit model
Mealy machine model
Moore machine model
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Sequential logic circuits

7. Sequential Circuit Models
Circuit type
Excitation
Output
Combinational
None
O = g(I)
Moore Machine
E = f (I, St)
O = g(St)
Mealy Machine
O = g(I, St)
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Sequential logic circuits

8. Sequential logic circuits
Memory Devices
Latches A latch is a memory element whose excitation signals control the state of the device. A latch has two stages set and reset. Set stage sets the output to 1. Reset stage set the output to 0.
Flip-flops A flip-flop is a memory device that has clock signals control the state of the device.
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Sequential logic circuits

9. Sequential logic circuits
Latch
Flip-flop
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Sequential logic circuits

10. Latch and Flip-Flop Devices
# of Elements
Description
74LS73A 2
Negative-edge triggered JK flip-flop with clear
7474
Positive-edge triggered D flip-flop with preset and clear
74LS75 4
D Latch with enable
7476
Pulse-edge triggered JK flip-flop with preset and clear
74111
Master-slave JK flip-flop with preset, clear, and data lock out
74116
4-bit hazard-free D latch with clear and dual enable
74175
Positive-edge triggered D flip-flop with clear
74273 8
74276
Negative-edge triggered JK flip-flop with preset and clear
74279
SR latch with active-low inputs
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Sequential logic circuits

11. Sequential logic circuits
Inverter Chains
Ring oscillator
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Sequential logic circuits

12. Sequential logic circuits
Latches
RS Latch
The RS latch is the basic memory element consists of two cross-coupled NOR gates. It has two input signals, S set signal and R reset signal. It also has two outputs Q and Q'; and two states, a set state when Q = 1 and a reset state when Q = 0 (Q' = 1)
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Sequential logic circuits

13. Sequential logic circuits1 S R Q
hold 1
0 reset
1 set
unstable
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Sequential logic circuits

14. Sequential logic circuits
Theoretical state diagram of cross-coupled NOR gates
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Sequential logic circuits

15. Sequential logic circuits
Observed state diagram of cross-coupled NOR gates
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Sequential logic circuits

16. RS Latch excitation table
Q(t)
Q(t+1)
Hold 1
Reset
Q(t+1) = S(t) + R'(t)Q(t)
Set
Q+ = S+ R'Q X
Forbidden
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Sequential logic circuits

17. Sequential logic circuits1 S R Q
unstable 1
0 reset
1 set
hold
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Sequential logic circuits

18. State, Clock, Setup Time, and Hold Time
The Clocking event can be either from low to high or from high to low. The input signal around clocking event must remain unchanged in order to have a correct effect on the outcome of the new state.
Tsu: the minimum time interval preceding
the clocking event during the input signal
must remain unchanged
Th: the minimum time interval after edge
of the clocking event during the input signal
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Sequential logic circuits

19. Timing Diagram of RS-Latch
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Sequential logic circuits

20. Sequential logic circuits
JK Latch S R
Q(t)
Q(t+1)
Hold 1
Reset
Set
Q+ = K'Q+ JQ'
toggle
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Sequential logic circuits

21. Level-Sensitive Latches
A level-sensitive latch is a latch with an additional enable input.
RS latch
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Sequential logic circuits

22. Sequential logic circuits
RS Latch with Enable C S R
Q(t)
Q(t+1) X
Hold 1
Reset
Set
toggle
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Sequential logic circuits

23. Sequential logic circuits
D Latch C D
Q(t)
Q(t+1) X
Hold 1
Reset
Set
Q+ = D
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Sequential logic circuits

24. Sequential logic circuits
Flip-Flops
A flip-flop is a level-sensitive latch with a clock input.
RS flip-flop
Q+ = S +R'Q
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Sequential logic circuits

25. Sequential logic circuits
T (Toggle) flip-flop D
Q(t)
Q(t+1)
Hold 1
Toggle
Q+ = TQ' + T'Q
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Sequential logic circuits

26. Master Slave Flip-Flops
A master slave flip-flop consists of two latches and an inverter.
Master-slave RS flip-flop
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Sequential logic circuits

27. Master-Slave JK Flip-Flops
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Sequential logic circuits

28. Sequential logic circuits
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Sequential logic circuits

29. Positive Edge-Triggered Flip-Flops
Positive edge-triggered RS flip-flop timing diagram
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Sequential logic circuits

30. Sequential logic circuits
Positive edge-triggered JK flip-flop timing diagram
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Sequential logic circuits

31. Sequential logic circuits
Positive edge-triggered D flip-flop timing diagram
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Sequential logic circuits

32. Positive Edge-Triggered Timing
A circuit that generates a positive edge-triggered timing signal can be constructed as follows:
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Sequential logic circuits

33. When inputs are sampled
Type
When inputs are sampled
When outputs are valid
Unclocked latch
Always
Propagation delay from input change
Level-sensitive latch
Clock high
Positive-edge latch
Clock low-to-high transition
Propagation delay from rising edge of clock
Negative-edge latch
Clock high-to-low transition
Propagation delay from falling edge of clock
Master/slave flip-flop
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Sequential logic circuits

34. Sequential logic circuits
Exercises
page 425, , 6.9, 6.10, 6.12, 6.13, 6.14, 6.17, 6.24, 6.25
CS Digital Logic
Sequential logic circuits