S UB -N YQUIST S AMPLING DSP & S UPPORT C HANGE D ETECTOR M IDTERM PRESENTATION S UB -N YQUIST S AMPLING DSP & S UPPORT C HANGE D ETECTOR M IDTERM PRESENTATION Performed by: Omer Kiselov Daniel Primor Winter 2010 :Supervised by Moshe Mishali Inna Rivkin High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

O UTLINE Algorithms in the systems Testing methods Functional Architecture Entity Definition Full System Architecture Resources Estimation Goals for future Work environment Gantt Chart

T HE W HOLE S YSTEM AND M AIN OBJECTIVE High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

To implement in hardware (on FPGA) a DSP to reconstruct the digital signal of the samples given by the expand To implement a Support Change Detector which identify the spectral support changes. The DSP & Support Change Detector Project Goals High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

The DSP Computation Algorithm High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering QR Decomposition As matrix R matrix Inverse Inv(R)*transpose(Q) Pseudo Inverse Of As Matrix Multiply Pinv(A)*Samples Y Y Analog Samples Digital Samples

M ATHEMATICAL A LGORITHM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

Adding an extra support to the matrix As. After Pseudo inverse the “Control Vector” is multiplied by 12 samples The results are summed up If the Energy level is high we get a support change. The support change signal is up to ‘1’ for a single clock cycle. The Support Change Detector Algorithm High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

S IMULATIONS Floating point simulations  The algorithm in basic hardware implementation possible functions Fixed point simulations  Word length : 18 bit, 12 for fraction  The algorithm with sliced R matrix High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

M AIN E NTITY I NTERFACE DSP & SCD High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL Memory interface Expander interface CTF interface

High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL I NTEFACE B EHAVIOR The Expander Sends The signals serially and valid while they are TRUE. The CTF sends a Valid bit and one clock cycle later send the support serially one by one after which the valid drops. It first sends the support amount one clock after valid simultaneously with the first support organ. The memory in the ordinary memory access. There are 3 clocks with hopefully 12 times the main clock in speed and 4 times the main clock in speed. Any faster clock will be appreciated.

MAIN BLOCK DIAGRAM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL

DSP BLOCK DIAGRAM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical EngineeringInputs HDL

DSP BLOCK DIAGRAM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL

DSP BLOCK DIAGRAM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL

DSP BLOCK DIAGRAM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL

DSP BLOCK DIAGRAM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL

S UPPORT CHANGE DETECTOR BLOCK DIAGRAM High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering HDL

R ESOURCES E STIMATION Multipliers: QR Decomposition needs one divide unit and one square root unit Other units don’t require arithmetic units Memory Estimation  The calculation matrixes (4) are saved in serial on chip FIFOs, with wordlength of 24X18bit=432bit, depth of 32 words  The Pseudo Inverse matrixes (current and last)are saved in on chip RAM, 2X24X24X18bit=20,736bit  The support is saved serially in on chip FIFO 12X7 bits  The support number is saved in the controller.  The samples are saved in on chip FIFO, including bit from SCD that shows if there is a change in the support, 227bit wordlength and depth of 64 words  In QR Decomposition: 4X18bit=72bit for Beta (number for calculation), 2X24X18bit=864bit for vectors, 2X24X24X18bit=20,736bit for temporary matrixesIn matrix multiplier: 2X24X24X18bit=20,736bit for temporary matrixes.  In samples multiplier: 2X24X18bit=864bit for samples Samples Multiplier Matrix MultiplierMatrix InverseQR Decomposition 48, uses Two Sum of Four mode 24, uses Two Sum of Four mode 2051

P ROJECT P ART A G OALS Until the end of the first part of the project:  To finish the implementation of the DSP & Support Change Detector in VHDL.  The system must pass a full simulation in ModelSim and perform (in flying colors! )  To reach the minimal acceptable mark of energy for the support change detector via simulation in Matlab. (Tradeoff – false alarm to miss detection) High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

B OUNDARIES I N I MPLEMENTATION We are to implement the device for the stratix III FPGA which has limited resources. High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering Device Multipliers 9x912x1218x1836x36 18X18 Complex 18X18 Sum of Mults EP3SE Stratix III breakdown Memory resources 1040X9k 48X144k 6750X0.64k

S IMULATION AND D ESIGN T OOLS High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering

Gantt Chart High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering * already done * in process * not approached yet

High speed digital systems laboratory Technion - Israel institute of technology department of Electrical EngineeringQuestions? Thank you very much!