1. Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Written by: Haim Natan Benny Pano Supervisor: Gregory Mironov

2. Designing and implementing an FPGA circuitry that inverses a matrix by using a Monte-Carlo based algorithm.

3. Input: * A 625x625 matrix Output: *A 625x625 inversed matrix Matrix Inverter Inverted matrix

4. The matrix will be of size 625x625 Matrix elements will be of type 64 bits double precision floating point The inverted matrix should be accurate as much as possible Calculation time < 20ms

5. The algorithm (simplified version) b i,j := 0; For c := 1 to N do { k 0 := i ; w 0 := 1 ; For t := 1 to T do { k t := MP( k t-1 ) ; w t := sign(d k t-1,k t ) * w t-1 * E k t-1 ; if k t = j then b i,j += w t ; } b i,j /= N ; N – number of markov chains T – length of each chain b – an inversed element MP() – a chain generator

6. The algorithm (continued) D = I – A E i = Σ j | d i,j | P is a transition probability matrix such that p i,j = | d i,j | / E i

7. Implementation Guide-lines Loop unroll (for c and t) Pipeline Use built-in multipliers Parallelize operations Cut out the fat

8. Basic Flow Diagram RAM A Pre Algorithm RAM P, (E) Monte-Carlo Algorithm Chain Generator P k (E) FPGA RAM B

9. Initial algorithm architecture MP SW A MP SW A k = i E1E1 EnEn 0 MP SW A b i,j T

10. Switch & Accumulator K in T in T out K out E in R in E out R out SW E out = E in R out = R in K out = K in If R in = K in Then T out = E in Else T out = T in K in W int C in V in C out V out A * W in W out T in C out = C in W out = W in * T in W int = W out If C in = K in Then V out = V in + W int Else V out = V in

11. Past Achievements 32x32 Matrix 8-bit Fixed Point T = 8 Time < 1ms Close to maximum utilization of Virtex II

12. To-do List Floating point arithmetic units Algorithm Markov chain generator Simulation Synthesis VHDL