1. By: Daniel BarskyNatalie Pistunovich Supervisors: Rolf HilgendorfInna Rivkin

2.  Previous work  Test environment description  Test results  Conclusions  Future work

4. Memory Controller...... A†A† CTF Expander DSP Support Change Detector Q-Frame OMP FPGA 1FPGA 2FPGA 3 73% 98% 75%

5. Timeline New Incoming Sample Expander Delay Q-Frame Delay 3.5usec OMP Delay 11usec Pseudo-Inverse Delay 5usec Reconstruction Delay Sample ready For reconstruction  Reconstruction Delay:  Expander - ~15 cycles (@120MHz)  CTF – ~1450 cycles (@120 MHz)  DSP - ~500 cycles (@120 MHz)

7. txt Filter Coefficients txt A Matrix txt Beta General Data txt Beta txt Filter Coefficients txt A Matrix

8. txt Input Data txt N N_frame txt Threshold txt Support txt Input Data txt N N_frame txt Threshold txt Support Dataset_1Dataset_2Dataset_3

9. VHDL Matlab_pack...\General Data …\Dataset_1 …\Dataset_2 …\Dataset_3 VHDL Matlab_pack

10. CTF Expander Supply Input Samples Input Samples N N_frame Threshold DSP SCD Samples FIFO Filter Coefficient FIFO Filter Coefficients Expanded Samples Recalculate Support Delayed Samples A Matrix β Record Reconstructed Data Simulation Controller

11.  Reads the filter coefficients from a file  Upon receiving a REQ, outputs a line of 7 coefficients and an ACK signal

12. CTF Expander Supply Input Samples Input Samples N N_frame Threshold DSP SCD Samples FIFO Filter Coefficient FIFO Filter Coefficients Expanded Samples Recalculate Support Delayed Samples A Matrix β Record Reconstructed Data Simulation Controller

13.  Reads from the files generated by Matlab:  The input samples  The N, N_frame, Threshold values  The correct support  Upon receiving a positive pulse on the OE signal, starts generating the input samples

14. FSM: Idle Opens the first Dataset files (input samples, N frame, threshold) and waits for an OE command Read next dataset Done OE Reads samples from the relevant dataset and feeds them to the expander Dataset i<3 done When the dataset samples are done, reads the samples and data for the next dataset Dataset 3 done When all samples are done, do nothing

15. CTF Expander Supply Input Samples Input Samples N N_frame Threshold DSP SCD Samples FIFO Filter Coefficient FIFO Filter Coefficients Expanded Samples Recalculate Support Delayed Samples A Matrix β Record Reconstructed Data Simulation Controller

16.  Read the appropriate data from A file  Upon receiving an address, output The appropriate data

17. CTF Expander Supply Input Samples Input Samples N N_frame Threshold DSP SCD Samples FIFO Filter Coefficient FIFO Filter Coefficients Expanded Samples Recalculate Support Delayed Samples A Matrix β Record Reconstructed Data Simulation Controller

18.  Upon receiving a WE, stores incoming samples from the expander  Upon receiving OE, outputs stored samples to the DSP for reconstruction  Maximum FIFO length – defined by a Generic  Actual FIFO length – 4294 samples (@20MHz)

19. CTF Expander Supply Input Samples Input Samples N N_frame Threshold DSP SCD Samples FIFO Filter Coefficient FIFO Filter Coefficients Expanded Samples Recalculate Support Delayed Samples A Matrix β Record Reconstructed Data Simulation Controller

20.  The main part of the testbench  Receives all status signals from all blocks, and sends control signals to all blocks  Consists of 3 FSMs – Expander FSM, CTF FSM, DSP FSM

21. Expander FSM: Init Initializes the expander and starts the process of loading the filter coefficients Wait Ready Phase Delay Ready Input Samples Done Counter Samples Done Waits until all coefficients have been loaded and the Expander is ready Raises the “Data Valid” signal while supplying zero samples (to generate phase shift) Raises the “Data Valid” signal and inputs real samples to the Expander Once the samples are finished, pauses the Expander

22. CTF FSM: Init Initializes the CTF Wait Ready Idle Ready Wait DSP Calculate Support Valid DSP Support ACK Support Change Waits until the CTF is ready Initiates the CTF support calculation and waits for a “Support Valid” signal Waits until DSP acknowledges the new support Waits until the SCD indicates a change in the support, upon which time it will initiate a recalculation of the support

23. DSP FSM: Wait Support DSP is ready and waiting for the CTF to calculate a new support Pseudo Inverse Support Change Reconst- ruction DSP is calculating a new Pseudoinverse matrix Pseudoinverse calculation done, samples from the Samples FIFO are used for reconstruction Support Valid Pseudoinverse Done Support Unchanged

39. LEsBlock RAM bits DSP Half- Blocks Previous Analysis (DSP Halfblocks) Expander43,8565Mbit448 CTF31,0006Mbit604 DSP62,9131.2Mbit752 Avaliable on Stratix III 260 203,52015Mbit768 (based on synthesis results of the different groups, including arcitecture blocks)

40. Expander CTF DSP 15 Cycles 1087 Cycles 29,823 Cycles Timeline New Incoming Sample Expander Delay CTF Delay 9.06usec DSP Delay 248.5usec Sample ready For reconstruction Timeline New Incoming Sample Expander Delay CTF Delay 14.5usec DSP Delay 5usec Sample ready For reconstruction Previous Evaluation:

41.  Support calculation is unstable, and extremely sensitive to input phase (relative to the NCO’s phase)  SCD is highly prone to misdetections & false positives!  The system seems to have more trouble with FM signals than with AM/sine

43.  Characterize the dependency of the support calculation on the input phase  Use fewer resources at a higher clock frequency at the reconstruction stage - in an attempt to squeeze it in with the Expander  Reimplement Pseudoinverse to share resources with the CTF, to fit them both in the same FPGA  Simulate & integrate implementation