Target Controller Electronics Upgrade Status P. Smith J. Leaver.

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Presentation transcript:

Target Controller Electronics Upgrade Status P. Smith J. Leaver

14/07/2015Imperial College 2 Control Electronics Upgrade Target controller upgrade - Stage 1: –Use existing designs for analogue circuitry –Replace digital control circuitry with USBDAQ –Recreate existing functionality, but with PC control interface Tasks: –Prepare analogue circuitry + housing (crate) –Design interface between USBDAQ & analogue boards –Implement controller logic in firmware –Write software drivers & GUI for user interaction

14/07/2015Imperial College 3 Analogue Circuitry Decided to leave existing controllers intact –If problems encountered during upgrade, have 2 fully functional backup systems New set of vero boards made: –Opto-isolated inputs –Optical & LED drivers –50R line drivers –D/A converter for target position –Optical analogue amplifiers for quadrature signals Required purchase of additional components (~£300) –Can recover approx. half this cost by component reuse at Stage 2 Analogue circuits will be reviewed/improved at Stage 2 & reimplemented as PCBs

14/07/2015Imperial College 4 Controller Crate Inter-board wiring to be completed when P Smith returns from PAC USBDAQ Interface Board

14/07/2015Imperial College 5 Controller Crate Panels 4 new panels required - currently being designed May be able to produce in-house at Sheffield –Workshop has new CNC tool with lettering capability Unfortunately omitted from original expenses estimate –Cost unsure, but should be reasonable Controller panel: –Enable switch added – cannot operate system until key inserted & turned –Other components just display status – reduced importance, as normal control/monitoring will be via USB

14/07/2015Imperial College 6 Interface Board FPGA on USBDAQ has (max) 3.3V IO Existing circuitry uses older technology, runs at 5V  Need active level translation -Control (FPGA → analogue circuitry): 36 channels -Feedback (analogue circuitry → FPGA): 10 channels Use custom interface board USBDAQ Analogue Circuitry 3.3V5V

14/07/2015Imperial College 7 3.3V → 5V Translation

14/07/2015Imperial College 8 5V → 3.3V Translation

14/07/2015Imperial College 9 Target Interface Board PCB Design PCB Dimensions: –10 cm x 10 cm –1.6 mm thick Layer stackup: Layer 1Signal Layer 2GND Layer 3Signal Layer 45V Layer 53.3V Layer 6Signal Layer 7GND Layer 8Signal

14/07/2015Imperial College 10 Target Interface Board PCB Design PCB Dimensions: –10 cm x 10 cm –1.6 mm thick Layer stackup: Layer 1Signal Layer 2GND Layer 3Signal Layer 45V Layer 53.3V Layer 6Signal Layer 7GND Layer 8Signal 3.3V → 5V 5V → 3.3V USBDAQ ConnectorsAnalogue Target Electronics Connectors

14/07/2015Imperial College 11 Target Interface Board PCB Design PCB Dimensions: –10 cm x 10 cm –1.6 mm thick Layer stackup: Layer 1Signal Layer 2GND Layer 3Signal Layer 45V Layer 53.3V Layer 6Signal Layer 7GND Layer 8Signal

14/07/2015Imperial College 12 Interface Board Production 4 boards: (Cheaper than 2!) –PCB Manufacture:£843 –Components:£ All parts have been delivered PCBs pass visual inspection/short circuit tests Component assembly to be performed by P Smith –Originally planned to use Cemgraft, but easier (in principle) & cheaper to do in-house –Also, good experience for P Smith (can determine whether practical to assemble Stage 2 PCBs in-house)

14/07/2015Imperial College 13 Firmware & Software Most ‘peripheral’ logic modules written & simulated –Quadrature counter –PWM generator –Delay generator –Timer for ISIS synchronisation –USB controller (provided with USBDAQ - functionality verified) P Smith & J Leaver to spend 2 days at IC next week –Establish common code base –Set out plan for implementing controller logic (& integration with existing modules) –Determine IO mapping Software development ‘on hold’ until details of controller firmware are finalised

14/07/2015Imperial College 14 Schedule Original schedule: –Stage 1 complete by mid-July This has slipped… Building new analogue boards took longer than reusing parts from old controllers –Caused ~1 week delay Need to populate Interface Board & complete inter-board wiring –Another ~1 week delay Limited availability of J Leaver in May (due to DAQ & Controls review) shifts software development to June (but should not affect final deadline) Not too worried by overall delay of a couple of weeks –Will have a better idea how this fits into the general scheme of things when installation schedule is finalised In the worst case, still have both old controllers as contingency!

14/07/2015Imperial College 15 Schedule