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Uli Schäfer JEM Status and plans Firmware Hardware status JEM1 Plans.

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Presentation on theme: "Uli Schäfer JEM Status and plans Firmware Hardware status JEM1 Plans."— Presentation transcript:

1 Uli Schäfer JEM Status and plans Firmware Hardware status JEM1 Plans

2 Uli Schäfer Firmware For JEM1 some modifications are required, mainly in I/O stages (DDR registers), block RAM, DLLs, multipliers, VME access, clock mirror, FCAL handling Work started  Incorrect behavioural simulation of input synchronisation stage of input FPGA : phase CLOCK40 / CLOCK80 (DLL) Speed problems on main processor Xilinx implementation software has problems interpreting timing constraints correctly when clock domains are crossed. CLOCK40 (global clock grid) on clock enable and multiplexer control lines in 80MHz domain >> generate ‘logic accessible clock’ running on general routing resources >> Leonardo  Xilinx XST synthesis

3 Uli Schäfer VME driver JEM1 block diagram Main Processor Input Processor 15* '921260 88 LVDS links 6 links per de-serialiser Config VME ROC TTC G G 15 x 6-channel de- serialisers : SCAN921260 4 Input daughter modules w. XC2V1500 ROC daughter Main Processor XC2V2000 DCS 6

4 Uli Schäfer Input Module top view Module size: 73x76mm 100R differential connectors for LVDS Connector (Bottom) Input Processor 6-ch deser. LVDS diff. FIO Main Control

5 Uli Schäfer JEM1 components: Input module Design complete by end of March Design files to manufacturer: April 2nd PCB production failed First try: misalignment of layers Second try : copper plating insufficient : 5μm on inner layer Third try : via plating insufficient : 13μm >> Submit the design to Rohde & Schwarz for both PCB production and assembly Expect back from assembly ~ August 7 (was end April!)

6 Uli Schäfer JEM1 components:ROC module ROC module carries ROC & G-links Clock mirror TTCdec Control FPGA CAN interface Configuration Status: currently under design. Configuration : parallel flash (CP-style) or SystemACE ? Finish by end September ?

7 Uli Schäfer JEM1 main boards JEM main board mainly consists of Backplane and daughter connectors Bus drivers (VME) and ECL line drivers/receivers Main processor (BGA 1.28mm pitch) Voltage converters Front panel connectors/LEDs Status: start design in September

8 Uli Schäfer Plans Continue to test interface to ROD Next RAL test mid July? –ROD tests –Full jet code tests (2 JEMs) ? JEM1 input daughters available Aug. 7 ROC daughter design finished end of September + 1month production JEM main board design finished November +1month production We do not expect to have the new JEMs available for test before end 2003 Keep JEM0s up and running for slice test until JEM1 successfully built and tested

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