Paulo Moreira & Jorgen Christiansen CERN - Geneva, Switzerland CMOS Technology Paulo Moreira & Jorgen Christiansen CERN - Geneva, Switzerland This part is compressed set of transparencies from Paulo Moreira: http://paulo.moreira.free.fr/ Paulo Moreira CMOS technology

Outline Part 1: Basic CMOS technology (from Paulo Moreira) How it all started CMOS Transistors Parasitics The CMOS inverter Technology Scaling Paulo Moreira CMOS technology

Introduction First point contact transistor (germanium), 1947 John Bardeen and Walter Brattain Bell Laboratories Audion (Triode), 1906 Lee De Forest 1947 1906 First integrated circuit (germanium), 1958 Jack S. Kilby, Texas Instruments transistors resistors and capacitors Intel Pentium II, 1997 Gate Length: 0.35, Clock: 233MHz Number of transistors: 7.5 M 1958 1997 Paulo Moreira CMOS technology

The world is becoming digital Digital processing is taking over: Computing, DSP Instrumentation Control systems Telecommunications Consumer electronics But analog is still needed in critical parts: Amplification of weak signals A/D and D/A conversion Radio Frequency (RF) communications As digital systems become faster and circuit densities increase the analog side of digital circuits are becoming important Crosstalk, Delays in R-C wires, Jitter, matching, substrate noise, etc. Paulo Moreira CMOS technology

“Moore’s Law” “Integration complexity doubles every three years” 42 M transistors Number of transistors doubles every 2.3 years (acceleration over the last 4 years: 1.5 years) Increase: ~20K 2.25 K transistors (From: http://www.intel.com) “Integration complexity doubles every three years” Gordon Moore, Fairchild1965 Paulo Moreira CMOS technology

Trends . Paulo Moreira CMOS technology

Driving force: Economics Traditionally, the cost/function in an IC is reduced by 25% to 30% a year. To achieve this, the number of functions/IC has to be increased. This demands for: Increase of the transistor count Decrease of the feature size (contains the area increase and improves performance) Increase of the clock speed Increase productivity: Increase equipment throughput Increase manufacturing yields Increase the number of chips on a wafer: reduce the area of the chip: smaller feature size & redesign Use the largest wafer size available Paulo Moreira CMOS technology

“CMOS building blocks” “Making Logic” Silicon switches: The NMOS Its mirror image, the PMOS Electrical behavior: Strong inversion Model How good is the approximation? Weak inversion Gain and inversion Paulo Moreira CMOS technology

“Making Logic” Logic circuit “ingredients”: Power source Switches Power gain Inversion Power always comes from some form of external EMF generator. NMOS and PMOS transistors: Can perform the last three functions They are the building blocks of CMOS technologies! Paulo Moreira CMOS technology

Silicon switches: the NMOS Paulo Moreira CMOS technology

Silicon switches: the NMOS Above silicon: Thin oxide (SiO2) under the gate areas; Thick oxide everywhere else; Paulo Moreira CMOS technology

Silicon switches: the PMOS Paulo Moreira CMOS technology

MOSFET equations Cut-off region Linear region Saturation Oxide capacitance Process “transconductance” 0.24mm process tox = 5nm (~10 atomic layers) Cox = 5.6fF/mm2 Paulo Moreira CMOS technology

MOS output characteristics Cut off: Vgs < Vt Linear region: Vds<Vgs-VT Voltage controlled resistor Saturation region: Vds>Vgs-VT Voltage controlled current source Deviation from the ideal current source caused by channel modulation Vds Vgs Ids G D S Paulo Moreira CMOS technology

MOS output characteristics Paulo Moreira CMOS technology

MOS output characteristics Paulo Moreira CMOS technology

Bulk effect The threshold depends on: Gate oxide thickness Doping levels Source-to-bulk voltage When the semiconductor surface inverts to n-type the channel is in “strong inversion” Vsb = 0  strong inversion for: surface potential > -2F Vsb > 0  strong inversion for: surface potential > -2F + Vsb Paulo Moreira CMOS technology

Bulk effect W = 24mm L = 48mm Vsb = 0V Vsb = 1 V Paulo Moreira CMOS technology

Mobility The current driving capability can be improved by using materials with higher electron mobility Paulo Moreira CMOS technology

Is the quadratic law valid? Quadratic “law” valid for long channel devices only! Paulo Moreira CMOS technology

Weak inversion Is Id=0 when Vgs<VT? For Vgs<VT the drain current depends exponentially on Vgs In weak inversion and saturation (Vds > ~150mV): where Used in very low power designs Slow operation Paulo Moreira CMOS technology

Gain & Inversion Gain: Inversion: The gain cell load can be: Signal regeneration at every logic operation “Static” flip-flops “Static” RW memory cells Inversion: Intrinsic to the common-source configuration The gain cell load can be: Resistor Current source Another gain device (PMOS) Paulo Moreira CMOS technology

Simple MOS model for digital designers The MOS transistor “is” a capacitor whose voltage controls the passage of current between two nodes called the source and the drain. One of the electrodes of this capacitor is called the gate, the other the source. The “way” the current flows between the source and the drain depends on the gate-to-source voltage (Vgs) and on the drain-to-source voltage (Vds). Vds Vgs Ids G D S G D Vgs Cgs Ids Vds S S Paulo Moreira CMOS technology

Simple model Ids Z= Vds Vgs Cgs Vds Vgs If the gate-to-source voltage (Vgs) is less than a certain voltage, called the threshold voltage (Vth), no current flows in the drain circuit no matter what the drain-to-source voltage (Vds) is! This is the actual definition of threshold voltage Vth. That is, Ids = 0 for Vgs < Vth This is the same as saying that the drain circuit is an infinite impedance (an open circuit)! Ids D G D G Z= Vds Vgs Cgs Vds Vgs S S S S Paulo Moreira CMOS technology

Simple model Ids Ids Vds Vgs Cgs I Vds Vgs If the gate-to-source voltage (Vgs) is bigger than the threshold voltage (Vth) and the drain-to-source voltage (Vds) is bigger than Vgs – Vth then the drain current only depends on the gate overdrive voltage (Vgs – Vth) That is, the drain circuit behaves as an “ideal” voltage controlled current source: Ids Ids D G D G Vds Vgs Cgs I Vds Vgs S S S S Paulo Moreira CMOS technology

Simple model Ids Vds Cgs R Vgs If the gate-to-source voltage (Vgs) is bigger than the threshold voltage (Vth) and the drain-to-source voltage (Vds) is smaller than Vgs – Vth then the drain current depends both on the gate overdrive voltage (Vgs – Vth) and the drain-to-source voltage (Vds) That is, the drain circuit behaves as a voltage controlled resistor: Vds Vgs Ids Cgs G D S R Paulo Moreira CMOS technology

Simple model For PMOS transistors the same concepts are valid except that: All voltages are negative (including Vth) Were we used bigger than you should use smaller than The drain current actually flows out of the transistor instead of into the transistor. REMEMBER! This is a very simplistic model of the device! For detailed analog simulations one relies on complicated SPICE models with many parameters defined by the technology and transistor size However, it will allow us to understand qualitatively the behaviour of CMOS logic circuits! Even some conclusions will be based on such a simple model. Paulo Moreira CMOS technology

We digital designers care about delays In MOS circuits capacitive loading is the main cause. (RC delay in the interconnects will be addressed latter) Capacitance loading is due to: Device capacitance Interconnect capacitance Assuming VT = 0 Paulo Moreira CMOS technology

MOSFET capacitances MOS capacitances have three origins: Ldrawn Leff The basic MOS structure The channel charge The pn-junctions depletion regions Ldrawn Leff Paulo Moreira CMOS technology

MOS structure capacitances Source/drain diffusion extend below the gate oxide by: xd - the lateral diffusion This gives origin to the source/drain overlap capacitances: Gate-bulk overlap capacitance: Drain Paulo Moreira CMOS technology

MOS structure capacitances 0.24 mm process NMOS L(drawn) = 0.24 mm L(effective) = 0.18 mm W(drawn) = 2 mm Co (s, d, b) = 0.36 fF/mm Cox = 5.6 fF/mm2 Cgso = Cgdo = 0.72 fF Cgbo = 0.086 fF Cg = 2.02 fF Note that: For small L devices the overlap capacitances are becoming as important as the “intrinsic” gate capacitance (Cg = Weff  Leff  Cox) Paulo Moreira CMOS technology

Channel capacitance The channel capacitance is nonlinear Its value depends on the operation region Its formed of three components: Cgb - gate-to-bulk capacitance Cgs - gate-to-source capacitance Cgd - gate-to-drain capacitance Operation region C gb gs gd Cutoff ox W Leff Linear (1/2) C Saturation (2/3) C Paulo Moreira CMOS technology

Junction capacitances Csb and Cdb are diffusion capacitances composed of: Bottom-plate capacitance: Side-wall capacitance: Paulo Moreira CMOS technology

“Building a full MOS model MOS process parasitics pn-Junction diodes Depletion capacitance Source/drain resistance MOS Model Parasitic bipolars Paulo Moreira CMOS technology

MOS Parasitics In a CMOS process the devices are: PMOS FETs NMOS FETs + unwanted (but ubiquitous): pn-Junction diodes parasitic capacitance parasitic resistance and parasitic bipolars parasitic inductance Paulo Moreira CMOS technology

Parasitics or useful? Resistors Capacitors Inductors Diodes Bipolar transistors Are useful circuit elements for analogue circuit design. Some technologies offer the possibility of manufacture such devices under controlled conditions. Paulo Moreira CMOS technology

pn-Junction diodes pn – Junction diodes: Provide isolation between devices (if reversed biased) Can be used to implement: band-gap circuits (if forward biased) variable capacitors clamping devices level shifting Are extremely useful as Electro Static Discharge (ESD) protection devices. Paulo Moreira CMOS technology

CMOS devices Remember: Every source and drain creates a pn-junction pn-junctions must be reversed biased to provide isolation between devices Reversed biased pn-junctions display parasitic capacitance Aluminium contact (Oxide cut) Paulo Moreira CMOS technology

pn-Junctions diodes Any pn-junction in the IC forms a diode Majority carriers diffuse from regions of high to regions of low concentration The electric field of the depletion region counteracts diffusion In equilibrium there is no net flow of carriers in the diode Paulo Moreira CMOS technology

Source/drain resistance Scaled down devices  higher source/drain resistance: In sub- processes silicidation is used to reduce the source, drain and gate parasitic resistance 0.24 mm process R (P+) = 4 W/sq R (N-) = 4 W/sq Paulo Moreira CMOS technology

Basic MOSFET model For designing we rely on simulators (SPICE) with appropriate models and parameters given by technology supplier. Rds Paulo Moreira CMOS technology

CMOS parasitic bipolar Every p-n-p or n-p-n regions form parasitic bipolar transistors. In standard MOS circuits these devices must be turned off. If not a latchup (short circuit) can occur For some applications (like bandgap circuits) these devices can be used. But, better know what you are doing… For digital designs we “forget” about this Paulo Moreira CMOS technology

How do we make digital from this ? Logic levels MOST – a simple switch The CMOS inverter: DC operation Dynamic operation Propagation delay Power consumption Layout Paulo Moreira CMOS technology

CMOS logic: “0” and “1” Logic circuits process Boolean variables Logic values are associated with voltage levels: VIN > VIH  “1” VIN < VIL  “0” Noise margin: NMH=VOH-VIH NML=VIL-VOL Paulo Moreira CMOS technology

The MOST - a simple switch Paulo Moreira CMOS technology

The CMOS inverter Paulo Moreira CMOS technology

The CMOS inverter Paulo Moreira CMOS technology

The CMOS inverter Regions of operation (balanced inverter): Vin n-MOS p-MOS Vout 0 cut-off linear Vdd VTN<Vin<Vdd/2 saturation linear ~Vdd Vdd/2 saturation saturation Vdd/2 Vdd-|VTP|>Vin>Vdd/2 linear saturation ~0 Vdd linear cut-off 0 Paulo Moreira CMOS technology

The CMOS inverter CL=250fF Paulo Moreira CMOS technology

The CMOS inverter Propagation delay Main origin: load capacitance To reduce the delay: Reduce CL Increase kn and kp. That is, increase W/L Paulo Moreira CMOS technology

The CMOS inverter CMOS power budget: Dynamic power consumption: Charging and discharging of capacitors Short circuit currents: Short circuit path between power rails during switching Leakage Leaking diodes. Leaking transistors: Sub-threshold currents In the future devices gate leakage current!? Paulo Moreira CMOS technology

The CMOS inverter The dynamic power dissipation is a function of: Frequency Capacitive loading Voltage swing To reduce dynamic power dissipation Reduce: CL Reduce: f Reduce: Vdd  The most effective action CMOS logic: no static power consumption! Paulo Moreira CMOS technology

The CMOS inverter Paulo Moreira CMOS technology

The CMOS inverter substrate contact (p+) n-well contact (n+) n-well polysilicon diffusion contacts n+ diffusions p+ diffusions polysilicon contacts Paulo Moreira CMOS technology

Scale between N and P MOS How to make a buffer Paulo Moreira CMOS technology

CMOS technology An Integrated Circuit is an electronic network fabricated in a single piece of a semiconductor material The semiconductor surface is subjected to various processing steps in which impurities and other materials are added with specific geometrical patterns The fabrication steps are sequenced to form three dimensional regions that act as transistors and interconnects that form the switching or amplification network Paulo Moreira CMOS technology

Lithography Lithography: process used to transfer patterns to each layer of the IC Lithography sequence steps: Designer: Drawing the “layer” patterns on a layout editor Silicon Foundry: Masks generation from the layer patterns in the design data base Masks are not necessarily identical to the layer patterns but they are obtained from them. Printing: transfer the mask pattern to the wafer surface Process the wafer to physically pattern each layer of the IC Paulo Moreira CMOS technology

Lithography Basic sequence The surface to be patterned is: spin-coated with photoresist the photoresist is dehydrated in an oven (photo resist: light-sensitive organic polymer) The photoresist is exposed to ultra violet light: For a positive photoresist exposed areas become soluble and non exposed areas remain hard The soluble photoresist is chemically removed (development). The patterned photoresist will now serve as an etching mask for the SiO2 Paulo Moreira CMOS technology

Lithography The SiO2 is etched away leaving the substrate exposed: the patterned resist is used as the etching mask Ion Implantation: the substrate is subjected to highly energized donor or acceptor atoms The atoms impinge on the surface and travel below it The patterned silicon SiO2 serves as an implantation mask The doping is further driven into the bulk by a thermal cycle Paulo Moreira CMOS technology

Lithography The lithographic sequence is repeated for each physical layer used to construct the IC. The sequence is always the same: Photoresist application Printing (exposure) Development Etching Paulo Moreira CMOS technology

Lithography Patterning a layer above the silicon surface Paulo Moreira CMOS technology

Lithography Etching: Etching techniques: Process of removing unprotected material Etching occurs in all directions Horizontal etching causes an under cut “preferential” etching can be used to minimize the undercut Etching techniques: Wet etching: uses chemicals to remove the unprotected materials Dry or plasma etching: uses ionized gases rendered chemically active by an rf-generated plasma Paulo Moreira CMOS technology

Physical structure NMOS layout representation: Implicit layers: oxide layers substrate (bulk) Drawn layers: n+ regions polysilicon gate oxide contact cuts metal layers NMOS physical structure: p-substrate n+ source/drain gate oxide (SiO2) polysilicon gate CVD oxide metal 1 Leff<Ldrawn (lateral doping effects) Paulo Moreira CMOS technology

Physical structure PMOS layout representation: Implicit layers: oxide layers Drawn layers: n-well (bulk) n+ regions polysilicon gate oxide contact cuts metal layers PMOS physical structure: p-substrate n-well (bulk) p+ source/drain gate oxide (SiO2) polysilicon gate CVD oxide metal 1 Paulo Moreira CMOS technology

CMOS fabrication sequence 0. Start: For an n-well process the starting point is a p-type silicon wafer: wafer: typically 75 to 300mm in diameter and less than 1mm thick 1. Epitaxial growth: A single p-type single crystal film is grown on the surface of the wafer by: subjecting the wafer to high temperature and a source of dopant material The epi layer is used as the base layer to build the devices Advanced technologies use high resistively substrates (non-epi) 300 mm Paulo Moreira CMOS technology

CMOS fabrication sequence 2. N-well Formation: PMOS transistors are fabricated in n-well regions The first mask defines the n-well regions N-well’s are formed by ion implantation or deposition and diffusion Lateral diffusion limits the proximity between structures Ion implantation results in shallower wells compatible with today’s fine-line processes Paulo Moreira CMOS technology

CMOS fabrication sequence 3. Active area definition: Active area: planar section of the surface where transistors are build defines the gate region (thin oxide) defines the n+ or p+ regions A thin layer of SiO2 is grown over the active region and covered with silicon nitride Paulo Moreira CMOS technology

CMOS fabrication sequence 4. Isolation: Parasitic (unwanted) FET’s exist between unrelated transistors (Field Oxide FET’s) Source and drains are existing source and drains of wanted devices Gates are metal and polysilicon interconnects The threshold voltage of FOX FET’s are higher than for normal FET’s Paulo Moreira CMOS technology

CMOS fabrication sequence FOX FET’s threshold is made high by: introducing a channel-stop diffusion that raises the impurity concentration in the substrate in areas where transistors are not required making the FOX thick 4.1 Channel-stop implant The silicon nitride (over n-active) and the photoresist (over n-well) act as masks for the channel-stop implant Paulo Moreira CMOS technology

CMOS fabrication sequence 4.2 Local oxidation of silicon (LOCOS) The photoresist mask is removed The SiO2/SiN layers will now act as a masks The thick field oxide is then grown by: exposing the surface of the wafer to a flow of oxygen-rich gas The oxide grows in both the vertical and lateral directions This results in a active area smaller than patterned Paulo Moreira CMOS technology

CMOS fabrication sequence Silicon oxidation is obtained by: Heating the wafer in a oxidizing atmosphere: Wet oxidation: water vapor, T = 900 to 1000ºC (rapid process) Dry oxidation: Pure oxygen, T = 1200ºC (high temperature required to achieve an acceptable growth rate) Oxidation consumes silicon SiO2 has approximately twice the volume of silicon The FOX recedes below the silicon surface by 0.46XFOX Paulo Moreira CMOS technology

CMOS fabrication sequence 5. Gate oxide growth The nitride and stress-relief oxide are removed The devices threshold voltage is adjusted by: adding charge at the silicon/oxide interface The well controlled gate oxide is grown with thickness tox Paulo Moreira CMOS technology

CMOS fabrication sequence 6. Polysilicon deposition and patterning A layer of polysilicon is deposited over the entire wafer surface The polysilicon is then patterned by a lithography sequence All the MOSFET gates are defined in a single step The polysilicon gate can be doped (n+) while is being deposited to lower its parasitic resistance (important in high speed fine line processes) Paulo Moreira CMOS technology

CMOS fabrication sequence 7. PMOS formation Photoresist is patterned to cover all but the p+ regions A boron ion beam creates the p+ source and drain regions The polysilicon serves as a mask to the underlying channel This is called a self-aligned process It allows precise placement of the source and drain regions During this process the gate gets doped with p-type impurities Since the gate had been doped n-type during deposition, the final type (n or p) will depend on which dopant is dominant Paulo Moreira CMOS technology

CMOS fabrication sequence 8. NMOS formation Photoresist is patterned to define the n+ regions Donors (arsenic or phosphorous) are ion-implanted to dope the n+ source and drain regions The process is self-aligned The gate is n-type doped Paulo Moreira CMOS technology

CMOS fabrication sequence 9. Annealing After the implants are completed a thermal annealing cycle is executed This allows the impurities to diffuse further into the bulk After thermal annealing, it is important to keep the remaining process steps at as low temperature as possible Paulo Moreira CMOS technology

CMOS fabrication sequence 10. Contact cuts The surface of the IC is covered by a layer of CVD oxide The oxide is deposited at low temperature (LTO) to avoid that underlying doped regions will undergo diffusive spreading Contact cuts are defined by etching SiO2 down to the surface to be contacted These allow metal to contact diffusion and/or polysilicon regions Paulo Moreira CMOS technology

CMOS fabrication sequence 11. Metal 1 A first level of metallization is applied to the wafer surface and selectively etched to produce the interconnects Paulo Moreira CMOS technology

CMOS fabrication sequence 12. Metal 2 Another layer of LTO CVD oxide is added Via openings are created Metal 2 is deposited and patterned Paulo Moreira CMOS technology

CMOS fabrication sequence 13. Over glass and pad openings A protective layer is added over the surface: The protective layer consists of: A layer of SiO2 Followed by a layer of silicon nitride The SiN layer acts as a diffusion barrier against contaminants (passivation) Finally, contact cuts are etched, over metal 2, on the passivation to allow for wire bonding. Paulo Moreira CMOS technology

Advanced CMOS processes Shallow trench isolation n+ and p+-doped polysilicon gates (low threshold) source-drain extensions LDD (hot-electron effects) Self-aligned silicide (spacers) Non-uniform channel doping (short-channel effects) Paulo Moreira CMOS technology

Process enhancements Up to six metal levels in modern processes Copper for interconnections Stacked contacts and vias Chemical Metal Polishing for technologies with several metal levels For analogue applications some processes offer: capacitors resistors bipolar transistors (BiCMOS) Paulo Moreira CMOS technology

Yield Yield The yield is influenced by: the technology the chip area the layout Scribe cut and packaging also contribute to the final yield Yield can be approximated by: A - chip area (cm2) D - defect density (defects/cm2) Paulo Moreira CMOS technology

Design rules The limitations of the patterning process give rise to a set of mask design guidelines called design rules Design rules are a set of guidelines that specify the minimum dimensions and spacings allowed in a layout drawing Violating a design rule might result in a non-functional circuit or in a highly reduced yield The design rules can be expressed as: A list of minimum feature sizes and spacings for all the masks required in a given process Based on single parameter  that characterize the linear feature (e.g. the minimum grid dimension).  base rules allow simple scaling Paulo Moreira CMOS technology

Design rules Minimum line-width: Minimum spacing: smallest dimension permitted for any object in the layout drawing (minimum feature size) Minimum spacing: smallest distance permitted between the edges of two objects This rules originate from the resolution of the optical printing system, the etching process, or the surface roughness Paulo Moreira CMOS technology

Design rules Contacts and vias: minimum size limited by the lithography process large contacts can result in cracks and voids Dimensions of contact cuts are restricted to values that can be reliably manufactured A minimum distance between the edge of the oxide cut and the edge of the patterned region must be specified to allow for misalignment tolerances (registration errors) Paulo Moreira CMOS technology

Design rules MOSFET rules n+ and p+ regions are formed in two steps: the active area openings allow the implants to penetrate into the silicon substrate the nselect or pselect provide photoresist openings over the active areas to be implanted Since the formation of the diffusions depend on the overlap of two masks, the nselect and pselect regions must be larger than the corresponding active areas to allow for misalignments Paulo Moreira CMOS technology

Design rules Gate overhang: The gate must overlap the active area by a minimum amount This is done to ensure that a misaligned gate will still yield a structure with separated drain and source regions A modern process have thousands of rules to be verified Programs called Design Rule Checkers assist the designer in that task Paulo Moreira CMOS technology

Technology scaling Scaling objectives Scaling variables Scaling consequences: Device area Transistor density Gate capacitance Drain current Gate delay Power Power density Interconnects Paulo Moreira CMOS technology

Scaling, why is it done? Paulo Moreira CMOS technology

Technology scaling Technology scaling has a threefold objective: Increase the transistor density Reduce the gate delay Reduce the power consumption At present, between two technology generations, the objectives are: Doubling of the transistor density; Reduction of the gate delay by 30% (43% increase in frequency); Reduction of the power by 50% (at 43% increase in frequency); Paulo Moreira CMOS technology

Technology scaling How is scaling achieved? All the device dimensions (lateral and vertical) are reduced by 1/ Concentration densities are increased by  Device voltages reduced by 1/ (not in all scaling methods) Typically 1/ = 0.7 (30% reduction in the dimensions) Paulo Moreira CMOS technology

Technology scaling The scaling variables are: Supply voltage: Vdd  Vdd /  Gate length: L  L /  Gate width: W  W /  Gate-oxide thickness: tox  tox /  Junction depth: Xj  Xj /  Substrate doping: NA  NA   This is called constant field scaling because the electric field across the gate-oxide does not change when the technology is scaled If the power supply voltage is maintained constant the scaling is called constant voltage. In this case, the electric field across the gate-oxide increases as the technology is scaled down. Due to gate-oxide breakdown, below 0.8µm only “constant field” scaling is used. Paulo Moreira CMOS technology

Scaling consequences Some consequences of 30% scaling in the constant field regime ( = 1.43, 1/ = 0.7): Device/die area: W  L  (1/)2 = 0.49 In practice, microprocessor die size grows about 25% per technology generation! This is a result of added functionality. Transistor density: (unit area) /(W  L)  2 = 2.04 In practice, memory density has been scaling as expected. (not true for microprocessors…) Paulo Moreira CMOS technology

Scaling consequences Gate capacitance: W  L / tox  1/ = 0.7 Drain current: (W/L)  (V2/tox)  1/ = 0.7 Gate delay: (C  V) / I  1/ = 0.7 Frequency   = 1.43 In practice, microprocessor frequency has doubled every technology generation (2 to 3 years)! This faster increase rate is due to highly pipelined architectures (“less gates per clock cycle”) Paulo Moreira CMOS technology

Scaling consequences Power: C  V2  f  (1/)2 = 0.49 Power density: 1/tox  V2  f  1 In practice due to the faster increase in frequency power density has also been increasing Active capacitance/unit-area: Power dissipation is a function of the operation frequency, the power supply voltage and of the circuit size (number of devices). If we normalize the power density to V2  f we obtain the active capacitance per unit area for a given circuit. This parameter can be compared with the oxide capacitance per unit area: 1/tox   = 1.43 In practice, for microprocessors, the active capacitance/unit-area only increases between 30% and 35%. Thus, the twofold improvement in logic density between technologies is not achieved: new microprocessors integrate relatively more memory that the previous generation. Paulo Moreira CMOS technology

Scaling consequences Interconnects scaling: Higher densities are only possible if the interconnects also scale. Reduced width  increased resistance Denser interconnects  higher capacitance To account for increased parasitics and integration complexity more interconnection layers are added: thinner and tighter layers  local interconnections thicker and sparser layers  global interconnections and power Interconnects are scaling as expected Paulo Moreira CMOS technology

Scaling consequences Parameter Constant Field Constant Voltage Supply voltage (Vdd) 1/ 1 Length (L) 1/ 1/ Width (W) 1/ 1/ Gate-oxide thickness (tox) 1/ 1/ Junction depth (Xj) 1/ 1/ Substrate doping (NA)   Electric field across gate oxide (E) 1  Depletion layer thickness 1/ 1/ Gate area (Die area) 1/2 1/2 Gate capacitance (load) (C) 1/ 1/ Drain-current (Idss) 1/  Transconductance (gm) 1  Gate delay 1/ 1/2 Current density  3 DC & Dynamic power dissipation 1/2  Power density 1 3 Power-Delay product 1/3 1/ Scaling Variables Device Repercussion Circuit Repercussion Paulo Moreira CMOS technology