1. CSCE 612: VLSI System Design Instructor: Jason D. Bakos

2. VLSI System Design 2 MOSFET Theory p-type body: majority carriers are holes accumulation mode V t depends on doping and t ox

3. VLSI System Design 3 Regions of Operation Gate to channel: V gs near source V gd near drain Switching delay is determined by: time required to charge/discharge gate time for current to travel across channel drain

4. VLSI System Design 4 Ideal I-V Characteristics Linear region(charge) (carrier velocity,  is mobility) (electric field)

5. VLSI System Design 5 Ideal I-V Characteristics Saturation region: into equation… cutoff linear saturation nmos pmos Holes have less mobility than electrons, so pmos’s provide less current (and are slower) than nmos’s of the same size Which parameters do we change to make MOSFETs faster?

6. VLSI System Design 6 Nonideal I-V Effects Velocity saturation and mobility degradation –Lower I ds than expected At high lateral field strength (V ds /L), carrier velocity stops increasing linearly with field strength At high vertical field strength (V gs / t ox ) the carriers scatter more often Channel length modulation –Saturation current increases with higher V ds Subthreshold conduction –Current drops exponentially when V gs drops below V t (not zero) Body effect –V t affected by source voltage relative to body voltage Junction leakage –S/D leaks current into substrate/well Tunneling –Gate current due to thin gate oxides Temperature dependence –Mobility and threshold voltage decrease with rising temperature

7. VLSI System Design 7 C-V Characteristics Capacitors are bad –Slow down circuit (need to use more power), creates crosstalk (noise) Gate is a good capacitor –Gate is one plate, channel is the other –Needed for operation: attracts charge to invert channel Source/drain are also capacitors to body (p-n junction) –Parasitic capacitance –“Diffusion capacitance” –Depends on diffusion area, perimeter, depth, doping levels, and voltage Make as small as possible (also reduces resistance)

8. VLSI System Design 8 Gate Capacitance Gate’s capacitance –Relative to source terminal –C gs =C OX WL –Assuming minimum length… –C gs =C per W –C per = C OX L = ( OX /t OX )L –Fab processes reduce length and oxide thickness simultaneously Keeps C per relatively constant 1.5 – 2 fF / um of width

9. VLSI System Design 9 Gate Capacitance Five components: Intrinsic: C gb, C gs, C gd Overlap: C gs(overlap), C gd(overlap) C 0 = WLC ox ParameterCutoffLinearSaturation C gb C0C0 00 C gs 0C 0 /22/3 C 0 C gd 0C 0 /20 SumC0C0 C0C0 2/3 C 0 C gsol =C gdol =0.2- 0.4 fF / um of width

10. VLSI System Design 10 Parasitic Capacitance Source and drain capacitance –From reverse-biased PN junction (diffusion to body) –C sb, C db –Depends of area and perimeter of diffusion, depth, doping level, voltage –Diffusion has high capacitance and resistance Made small as possible in layout –Approximately same as gate capacitance (1.5 – 2 fF / um of gate width) Isolated, shared, and merged diffusion regions for transistors in series

11. VLSI System Design 11 Switch-Level RC Delay Models Delay can be estimated as R * 6C FET passing weak value has twice the resistance