1. Junction Capacitances The n + regions forms a number of planar pn-junctions with the surrounding p-type substrate numbered 1-5 on the diagram. Planar junctions 2, 3 and 4 are surrounded by the p + channel stop implant. Planar junction 1 is facing the channel while the bottom planar junction 5 is facing the p-type substrate with doping N A. The junction types will be n + /p, n + /p +, n + /p + n + /p + and n + /p.

2. Junction Capacitances The voltage dependent source- substrate and drain-substrate junction capacitances are due to depletion charge surrounding the source or drain diffusion regions embedded in the substrate. The source-substrate and drain- substrate junctions are reverse biased under normal operating conditions. The amount of junction capacitance is a function of applied terminal voltages All junctions are assumed to be abrupt. Given that the depletion thickness is x d we can compute the depletion capacitance of a reverse biased abrupt pn-junction. Where N A and N D are the n-type and p-type doping densities respectively, V is the negative reverse bias voltage. The built-in junction potential is:

3. Junction Capacitances The junction is forward biased for a positive voltage V and reverse biased for a negative voltage V. The depletion region charge stored in this area in terms of x d is A stands for the junction area. The junction capacitance associated with the depletion region is defined as: If we differentiate the equation describing Q j with respect to the bias voltage we get C j. If the zero bias capacitance is: We can write the junction capacitance in a more general form as m is the gradient coefficient and is 0.5 for abrupt junctions and 1/3 for linearly graded junction profiles The value of the junction capacitance ultimately depends on the external bias voltage applied across the pn- junction.

4. Junction Capacitances The sidewalls of a typical MOSFET source or drain diffusion region are surrounded by a p + channel stop implant having a higher doping density than the substrate doping density N A. The sidewall zero bias capacitance is C j0sw and will be different from the previously discussed junction capacitance. The zero-bias capacitance per unit area can be found as follows: Where N A(sw) is the sidewall doping density,  0(sw) is the built- in potential of the sidewall junctions. All sidewalls in a typical diffusion structure have approximately the same junction depth x j. The zero bias sidewall junction capacitance per unit length is:

5. Non-Ideal I-V Effects (Summary) Miniaturization has led to modern devices having nonideal characteristics The saturation current increases less than quadratically with increasing V GS. Velocity saturation and mobility degradation are two of the effects that cause the non quadratic current increase with V GS. When carrier velocity ceases to increase linearly with field strength we have velocity saturation. The current I DS is lower than expected at high V DS. There are several sources of leakage that result in current flow when the transistor is expected to be OFF. The source and drain diffusion regions are form reverse biased diodes which experience junction leakage into the substrate or well. The current into the gate I G is ideal zero, however as gate oxide thickness is reduced electrons tunnel through the gate, causing some current.

6. Velocity Saturation The critical E-field at which scattering effects occur depends on the doping levels and the vertical electric field applied. Velocity saturation effects are less pronounced in pMOS devices. By increasing V DS the electrical field in the channel ultimately reaches the critical value and the carriers at the drain become velocity saturated. Further increasing V DS does not result in increased I D. The current saturates at I DSAT The behavior of the MOS transistor is better understood by analysis of the I- V curves.

7. Sub-Threshold Conduction Ideally at V GS < V T, I D = 0. The MOS device is partially conducting for gate voltages below the threshold voltage. This is termed sub-threshold or weak inversion conduction. In most digital applications the presence of sub-threshold current is undesirable. Why? ….most digital applications …. Does this mean some digital applications can tolerate sub-threshold currents? A Sub-threshold digital circuit manages to satisfy the ultra-low power requirement. How? What type of digital applications can benefit from this ultra low power design approach?