Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Floor Plan and Structural Verilog 02/26/2004 Design Manager: Rebecca Miller

Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done) More Accurate Transistor Count More Accurate Transistor Count Floor Plan Floor Plan Structural Verilog simulation debugging Structural Verilog simulation debugging  To be done Gate-level design Gate-level design Chip Layout Chip Layout Spice Simulation Spice Simulation

Design Decisions  Eliminated cipher registers by reusing text register  Reduced size of KeySub register to only hold 1 (current) key  Implemented Barrel Shifter using logic, rather than an additional ROM

Revised Architecture KeySub 56’b Register 32’b 32’b input demux Enc_ShiftL Dec_ShiftR IP -1 wiring PC-2 Wiring 56->48 IP wiring Text 64’b Register Expand 32->48 wiring S-Box 512 x 4’b P 48->32 wiring PC (wiring) Key Latch 2:1 mux 2:1 demux R_L Sub_rnd e/d D1/D1 txt_in ready key_in Sh_d Sh_e “R” “L” R L ’b 2:1 56’b 64-> 56 wr_en OUT ready 48 2:1 mux 32 64

I/O Pins  Required Inputs:  Provided Output : 32 bits data input at pins 32 bits data input at pins 1 bit reset at pin 1 bit reset at pin 1 bit encryption/decryption mode control at pin 1 bit encryption/decryption mode control at pin 32 bits data output at pins 32 bits data output at pins 1 bit ready at pin 1 bit ready at pin 1 bit givekey at pin 1 bit givekey at pin 1 bit clock at pin 1 bit clock at pin

Updated Transistor Counts and Area

Old Transistor CountNew Transistor Count SetupN/A2,672 Key Scheduler3,3452,184 Encryption10,4845,616 Program ControlN/A1,409 Total13,82911,881 Updated Transistor Counts and Area

PC (wiring) 64 -> 56 64’b 2:1 demux 56’b Key Latch 56’b 2:1 mux KeySub 56’b Register Des_ShiftREnc_ShiftL 32’b 2:1 demux 64’b 2:1 mux IP (wiring) Text 64’b Reg IP -1 Wiring Expand 48’b XOR 56’b 2:1 mux PC-2 wiring 56b -> 48b S-box 512 x 4’b P Wiring 32’b XOR Program Control (Instruction ROM) Input Output Floorplan um um 64’b 2:1 mux 125,534 um 2 =.126 mm 2 Density.09 Trans/um 2

Metal 1 – Horizontal local routing, Vdd, Gnd Metal 2 – Vertical local routing, Vdd, Gnd Metal 3 – Horizontal global routing, Clk, Rst Metal 4 – Vertical global routing, Clk, Rst M1 M2 M3 M4 Metal Usage

Structural Verilog Structural Verilog module crp(P, R, K_sub); output[1:32]P; input[1:32]R; input[1:48]K_sub; wire[1:48] E; wire[1:48] X; wire[1:32] S; assign E[1:48] = {R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5], R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11], R[12], R[13], R[12], R[13], R[14], R[15], R[16], R[17], R[16], R[17], R[18], R[19], R[20], R[21], R[20], R[21], R[22], R[23], R[24], R[25], R[24], R[25], R[26], R[27], R[28], R[29], R[28], R[29], R[30], R[31], R[32], R[1]}; // assign X = E ^ K_sub; xor(X[1], E[1], K_sub[1]); xor(X[2], E[2], K_sub[2]); xor(X[3], E[3], K_sub[3]); xor(X[4], E[4], K_sub[4]); xor(X[5], E[5], K_sub[5]); xor(X[6], E[6], K_sub[6]); xor(X[7], E[7], K_sub[7]); xor(X[8], E[8], K_sub[8]); xor(X[9], E[9], K_sub[9]); xor(X[10], E[10], K_sub[10]); xor(X[11], E[11], K_sub[11]); xor(X[12], E[12], K_sub[12]); sbox1 u0(.addr(X[01:06]),.dout(S[01:04]) ); sbox2 u1(.addr(X[07:12]),.dout(S[05:08]) ); sbox3 u2(.addr(X[13:18]),.dout(S[09:12]) ); sbox4 u3(.addr(X[19:24]),.dout(S[13:16]) ); sbox5 u4(.addr(X[25:30]),.dout(S[17:20]) ); sbox6 u5(.addr(X[31:36]),.dout(S[21:24]) ); sbox7 u6(.addr(X[37:42]),.dout(S[25:28]) ); sbox8 u7(.addr(X[43:48]),.dout(S[29:32]) ); assign P[1:32] = {S[16], S[7], S[20], S[21], S[29], S[12], S[28], S[17], S[1], S[15], S[23], S[26], S[5], S[18], S[31], S[10], S[2], S[8], S[24], S[14], S[32], S[27], S[3], S[9], S[19], S[13], S[30], S[6], S[22], S[11], S[4], S[25]}; endmodule

Problems and Questions  Permutation implemented by wiring may cause the wires to cross each other haphazardly. Is there any better way to implement this ?  Can we find a way to reduce the instruction set to loop one DES cycle?