1 H-Cal front-end ASIC Status LAL Orsay J. Fleury, C. de la Taille, G. Martin, L. Raux

2 Contents 1.SiPM Readout Prototype  DAC for gain Adjustement  1st option : Preamp+CRRC2 shaper  2nd option : Unipolar version: RC6 shaper:  Backup option : FLC_PHY3 2.Conclusion and perspectives  Production schedule  Production cost

3 SiPM Readout Prototype Chip 18-Channel Readout Chip Prototype  Technology AMS 0.8  m CMOS  DAC for Si PM Gain adjustment  Preamplifier + Shaper CRRC2  Unipolar solution  RC6 shaper  Track & Hold and multiplexed output (OPERA and FLC_PHY3) – Submitted in June 2004 – Received in September HV input 50Ω 100nF SiPM 100kΩ 100nF 8-bit DAC ASIC

4 DAC Schematic Adjustement gain DAC  8-bit DAC  excursion 1-5V  Based on ratioed mirror  OTA to avoid early effect (virtual ground)

5 Channel CRRC2 architecture for SiPM

6 Full simulation CRRC2 Calibration mode  Single photoelectron response  Cf=0.2pF ; τ =12ns  1 spe = 8.9 mV ; tp=40 ns  Noise : 720 µV rms Physics mode  MIP (=16pe) response  Cf=0.4pF ; Rc=5k ; τ =120ns  Gain = 12 mV/MIP ; tp=186ns  Noise = 570 µV rms  Cf=0.4pF; Rc=0 ; τ =180ns  Gain =14mV/MIP ; tp=150ns  Noise = 220 µV  Swing voltage: ~2.5V

7 RC6 architecture Unipolar architecture  RC6 Shaper Composed with 3 successive RC2 shaper τ=38ns OTA used for biasing Switch for calibration mode OFF calibration mode/ ON physics mode 5pF Vref 5.5pF OTA Gm=1uA/V 3.5kΩ 7kΩ 11pF 2.8kΩ Vin Vout

8 Full simulation RC6 Calibration mode  Single photoelectron response (1pe=160fC)  Gain 9mV/pe tp=30 ns  Noise : 1.4mV rms Physics mode  MIP (=16pe) response  Gain 17mV/MIP tp=200ns  Noise = 800 µV rms  Dynamic Range [1-125]MIP  Linearity <1%  Swing voltage: ~2.5V 1 MIP=16pe response 1 pe response 1 MIP response * MIP response

9 Backup: FLC_PHY3 No gain adjustement gain DAC No Variable shaping  No Calibration mode Measurement in progress 1000 chips available FLC_PHY3 50Ω 5kΩ 10pF 200pF

10 Schedule  Prototype Submission in June 2004  Prototype Delivery in September 2004  Test and validation with SiPM in October 2004  Production (1000chips) of the validated version could start in November 2004  Production Delivery expected in January 2005  Systematic chips test in February 2005  Chips available for the collaboration by March-April 2005

11 Production cost estimation Silicon : 1000 dies (area: ~10mm² )  2 wafers needed: 39 k Euros –Mask : 35 k Euros –Silicon : 4 k Euros Package : PQFP-100 : 4 k Euros Total : 43 k Euros Maybe possibility to share the production with other lab to decrease the production cost