1. R&D on large photodetectors and readout electronics FJPPL KEK/Orsay JE Campagne, S. Conforti, F. Dulucq, C. de La Taille, G. Martin-Chassard,, A. Nakomura, M. Tanaka, W Wei

2. R&D -two directions- [M. Tanaka]
France
Japan
Photon detector R&D
Readout system R&D
Photocathode
Scint
PMT
Hybrid Photon
Detector
HybridPMT
PMT
Low noise Preamp ASIC on HPD
+ Q-T/waveform recoder ASIC
Multichannel FE ASIC, close to the PMTs
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

3. cdlt FJPPL Neutrino PMM2 R&D
Motivation [M. Tanaka]
Application
High speed pattern recognition photon/track detection for high energy physics experiments under high intensity.
uSR spectrometer for material science
TOF PET/NMR hybrid etc
Detector
Low gain MAPMT/MHPD with Scintillator
MPPC
Function
Position detection or pattern matching
Flexiblility is important
Timing information 0.1n~1n smaller is better
Increase S/N
Position resolution
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

4. cdlt FJPPL Neutrino PMM2 R&D
Specification
Dynamic range
0.2pC~250pC
HEP application
10ph for MIP & Gain 5x10^5  0.2pC
PET
10000ph/event & Gain:5x10^4~5x10^5  25~250pC
Analog bandwidth ~ 150MHz
Gain 1,~10
Timing resolution 100ps
Hit rate : 100nsec(10nsec is better but limited by detector)
Channel : 16~32
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

5. PMm2 : large photodection area
“PMm2” (2006 – 2009), funded by the ANR : LAL, IPNO, LAPP and Photonis
Replace large PMTs (20”) by groups of smaller ones (12”)
central 16ch ASIC (MAROC like)
12 bit charge + 12 bit time
water-tight, common High Voltage
Only one wire out (DATA + VCC)
Target low cost
Reuse many parts from MAROC & SPIROC
Application : large water Cerenkov neutrino
1ns time resolution
High granularity
scalability
Joël Pouthas IPN Orsay
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

6. 3 discri thresholds (3*12 bits)
MAROC chip
Multi Anode Read Out Chip
64 channels, variable gain, 64 triggers, multiplexed digitized charge measurement
Performances:
Variable gain preamp PMs non-uniformity correction
Trigger at 1/3 p.e (= 106)
Dynamic range: 0 30 p.e (0 5pC)
Noise = 2fC
Linearity ~ 2%
Cross-talk < 1%
MAROC3 layout (November 2007)
Technology: AMS SiGe 0.35 mm
Die : 4 X 4.2 mm2
Hold signal
Photomultiplier
64 channels
Photons
Variable
Gain
Preamp.
Slow Shaper ns
S&H
Bipolar
Fast Shaper
Unipolar
Gain correction
64*6bits
3 discri thresholds (3*12 bits)
Multiplexed
Analog charge output
LUCID
3 DACs
12 bits
80 MHz encoder
64 Wilkinson 12 bit ADC
64 trigger outputs
Digital charge output
64 inputs
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

7. cdlt FJPPL Neutrino PMM2 R&D
Active board pictures
MAROC2 chip bounded at CERN
64 ch PMT
MAROC side
Lattice side
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

8. cdlt FJPPL Neutrino PMM2 R&D
SPIROC overview
Silicon Photomultiplier Integrated Read Out Chip
CALICE/A-HCAL read out
36 channels
30fC-300pC dynamic range
Charge measurement (15bits)
Time measurement (< 1ns)
Auto-trigger at 50fC (1/2 pe)
many SKIROC, HARDROC, and MAROC features re-used
First prototype received nov07
Collaboration with DESY
Felix Sefkow (DESY)
Production in 2009 for Eudet module
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

9. cdlt FJPPL Neutrino PMM2 R&D
PMm2 front-end ASIC
Complete front-end chip with 16 channels
To be submitted in June 2008
Technology : AMS SiGe 0.35 mm
Characteristics :
16 inputs preamplifier
Variable gain :1  5 (4bits) (common on 16 channels)
PMTs gain adjustment by a factor 4 (8 bits) (channel by channel)
Dynamic range : 0  300 pe
Good linearity (1%)
16 trigger outputs:
Fast shaper (t=15ns)
Low offset discriminator
Threshold provided by common 10bit DAC + 4bit DAC /channel (1/3 pe)
“OR” of 16 triggers output
1 digitized and multiplexed charge output :
Slow shaper with variable shaping time (t=50ns,100ns,200ns)
SCA with depth 2
A complete front end chip with 64 channels was submitted in last June and expected in this October.
I would like remind you of MAROC1 functionality blocks.
MAROC1 contains/is composed of a variable gain preamplifier to adjust the PM gain per channel from 0 to 4.
We have one multiplexed charge output where we can change the peaking time of slow shaper from 20ns to 200ns.
Otherwise there are 64 trigger outputs which can be due to Bipolar Fast shaper or Unipolar Fast Shaper
The unipolar Fast Shaper is followed by 3 discriminators to close to LUCID needs
Each threshold is fixed by internal DAC
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

10. cdlt FJPPL Neutrino PMM2 R&D
PMm2 front-end ASIC (2)
Coarse time measurement :
24 bit 10MHz
Step : 100ns
12 bit ADC for charge and fine time measurement :
Wilkinson type ADC
T&H on slow shaper for charge measurement
T&H on TDC ramp (100ns) for fine time measurement
2 discriminators with 12 bit ramp (100ms) as threshold
Serialization of digital output information :
Channel number - time stamp – fine time – charge
4bits 24bits bits bits
A complete front end chip with 64 channels was submitted in last June and expected in this October.
I would like remind you of MAROC1 functionality blocks.
MAROC1 contains/is composed of a variable gain preamplifier to adjust the PM gain per channel from 0 to 4.
We have one multiplexed charge output where we can change the peaking time of slow shaper from 20ns to 200ns.
Otherwise there are 64 trigger outputs which can be due to Bipolar Fast shaper or Unipolar Fast Shaper
The unipolar Fast Shaper is followed by 3 discriminators to close to LUCID needs
Each threshold is fixed by internal DAC
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

11. PMm2 ASIC ARCHITECTURE (analog part)
ramp
TDC
Internal read
MAROC
SPIROC
SPIROC like
NEW
Channel 16
Read
Channel 1
1 digital time
output
12 bits
ADC
Track
& hold
Vref SSH
1 digital charge
output
12 bits
ADC
CRRC2
Slow Shaper
(50 , 100,
200 ns)
Track
& hold
16 charge
inputs
Variable Gain
Amplifier
(1-5)
Hold
1 ext. Common Hold
variable
delay OR
1 OR output
Fast Shaper
(15ns)
Gain Correction
(8bits)
Vref FSH
Discri
16 Trigger outputs
Vref SSH
DAC
4 bits
24 bits
counter
10MHz
absolute time measurement
Bandgap
DAC
10 bits
Threshold
Common
bloc in
channel
bloc
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

12. cdlt FJPPL Neutrino PMM2 R&D
Conclusion
MAROC :
Measured circuit
Used for PMTs characterization
But low dynamic range
SPIROC :
Circuit with time measurement
Now in test
New development for PMm2:
Time measure (step 1ns)
High dynamic range
Serialized data output
Proto send in June 08
Chip test in fall 2008
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

13. OMEGA-KEK collaboration
Collaboration started in 2006 : nice exchanges between the two groups to optimize the design
Last visit of Tanaka-San in Orsay last january
Proposal to host japanese student in OMEGA end 2008/beg 2009
Common chip for PM readout and sharing building blocks. Chip will be submitted in june 08
Joint measurements in KEK and Orsay to start end 08
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D

14. cdlt FJPPL Neutrino PMM2 R&D
TEST BOARD
MAROC (COB)
64ch PM socket
USB port
GPIB port
Control Altera
You can see the test board with chip on board
The oscillation problem have been almost solved by chip on board
There are no longer oscillations at gain lower than 2
Paris 15 may 2008
cdlt FJPPL Neutrino PMM2 R&D