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Integrated electronic for SiPM KOBE – 29 June ‘07 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-Chassard, N. Seguin, L. Raux, S. Blin, P.

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Presentation on theme: "Integrated electronic for SiPM KOBE – 29 June ‘07 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-Chassard, N. Seguin, L. Raux, S. Blin, P."— Presentation transcript:

1 Integrated electronic for SiPM KOBE – 29 June ‘07 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-Chassard, N. Seguin, L. Raux, S. Blin, P. Barrillon, S. Callier LAL Orsay IN2P3-CNRS – Université Paris-Sud – B.P. 34 91898 Orsay cedex – France

2 Introduction  LAL microelectronic group is designing integrated front- end electronic for particle physics  Its know-how has evolved from low-noise front-end to multichannel read out ASICs system on chip design allowing low-cost high number of channel read-out  That talk will introduce a bunch of Front-end ASICs designed by LAL microelectronic group  4 ASICs suitable for SiPM read out will be presented : 2004 FLC_SIPM 2006 MAROC2 2006 HARDROC 2007 SPIROC

3 FLC_SIPM TCMT AHCAL beam ECAL 90 cm 120 cm FLC_SIPM has been designed to read out the CALICE AHCAL physics prototype It is also used in the TCMT read out

4 Tile HCAL testbeam prototype  1 cubic metre  38 layers, 2cm steel plates  8000 tiles with SiPMs  Electronics based on CALICE ECAL design, common back-end and DAQ DESY, Hamburg U, ITEP, MEPHI, LPI (Moscow) Northern Illinois LAL, Orsay Prague UK groups Tile sizes optimized for cost reasons ASICs: LAL Boards: DESY DAQ: UK DESY From Felix Sefkow’s talk

5 Gain and dark rate uniformity correction SiPM gain varies with the high voltage value  DAC to adjust gain CHANNEL BY CHANNEL from M.Danilov ITEP, Moscow

6 Gain and dark rate uniformity correction +HV Preamp input 50Ω 100nF SiPM 100kΩ 100nF 8-bit DAC ASIC High voltage on the cable shielding The input DACs allow to adjust HV channel by channel via slow control on the 8000 SiPM of the detector

7 Chip description  18-channel 8-bit DAC (0-5V)  18-channel front-end readout : Variable gain charge preamplifier (0.67 to 10 V/pC) Variable time constant CRRC 2 shaper (12 to 180 ns)  Track and hold  1 multiplexed output  Power consumption : ~200mW (supply : 0-5V)  Technology : AMS 0.8 m CMOS  Chip area : ~10mm²  Package : QFP-100

8 Channel architecture for SiPM readout 100nF 10pF Charge Preamplifier :  Low noise : 1300e- @40ns  Variable gain : 4bits : 0.67 to 10 V/pC CR-RC² Shaper : Variable time constant : 4 bits (12 to 180ns) 12ns  photoelectron measurement (calibration mode) 180ns  Mip measurement (physic mode) compatibility with ECAL read-out 12kΩ 4kΩ 24pF 12pF 3pF in 8pF4pF2pF1pF 40kΩ 8-bit DAC 0-5V ASIC Rin = 10kΩ 50Ω 100MΩ 2.4pF 1.2pF 0.6pF 0.3pF 0.1pF 0.2pF 0.4pF 0.8pF 6pF

9 MIP and photo-electron responses  Physics mode :  Cf=0.4pF- t=180ns - Rin ON  1 MIP = 16 p.e. injected  Vout = 23 mV @ tp = 160 ns  SLOW SHAPING FOR TRIGGER LATENCY  Calibration mode :  Cf=0.2pF - t=12ns - Rin OFF  1 SPE = 0.16pC injected  (0.6mV in 270pF)  Vout = 11 mV @ tp = 35 ns

10 Linearity measurement (physics mode) 0.5% -0.5% Voltage swing : ~2.1V Dynamic Range: 80 MIPs Linearity: <1%

11 Cross-talk measurement Set-up: Cf=0.4pF,  =180ns Channel-to-Channel cross-talk :  ~ 1-2‰ :negligible  2 contributions :  Capacitive coupling between neighboring channels  Long distance crosstalk in all channels (comes from a reference voltage) Non-Direct neighbouring channel x100 Sampling time Capacitive coupling contribution Direct neighbouring channel x100 Long Distance cross-talk contribution

12 FLC_SIPM results With russian SiPM With MPPC Felix Sefkow & al Tohru Takeshita & al -Physics results on such high number of channel are coming up -So far : -Noise as expected -Coherent noise very low -Dynamic range as expected

13 MAROC : a versatile front-end chip MAROC has been designed to read out 64-anode MA-PMT from HAMAMATSU. The first application is the ATLAS luminometer. Many other application have popped up (medical imaging, astrophysics, basically everything using MA-PMT)

14 MAROC : main features  64 Channels – designed to read out MA-PMT  Discrimination on each channel (3 thresholds)  Multi-gain preamp (0-4, 6 bits) tunable channel by channel to correct PMT gain non uniformity  Charge measurement and 12 bit multi-channel ADC working aside and independently of threshold detection (for cross measurement or calibration)  Perfectly suitable for SIPM read-out ATLAS luminometer using Hamamatsu MA-PMT Example of high integration

15 MAROC block diagram Hold signal 1 Photomultiplier 64 channels Photons Variable Gain Preamp. Variable Slow Shaper 20-100 ns S&H 1 Bipolar Fast Shaper Unipolar Fast Shaper Gain correction 64*6bits 3 discri thresholds (3*12 bits) Multiplexed Analog charge output LUCID S&H 2 3 DACs 12 bits 64 Wilkinson 12 bit ADC 64 trigger outputs Multiplexed Digital charge output 64 inputs Hold signal 2 LUCID FS choice 80 MHz encoder Cmd_LUCID EN_serializer MUX SUM of 7 fibres 9 Sums Or 64 SiPM Consumption : 130mW (~2mW/channel)

16 MAROC measurements Channel dispersion without any correction

17 Trigger efficiency : minimal injection The minimum input charge is 10 fC

18 DAC resolution All three DAC embedded have roughly the same response, DAC2 is presented here

19 shaper transient response The slow shaper transient response is presented here for different preamp gains

20 S-curves with threshold sweep DAC1 = 800 DAC1 = 1400 An example of trigger adjustment through the threshold (DAC step: 10)

21 50% efficiency charge vs threshold Charge threshold increases linearly with the DAC value

22 HARDROC presentation HARDROC has been designed to read out the CALICE RPC DHCAL technical prototype.

23 HARDROC main features  Full power pulsing  Digital memory: Data saved during bunch train.  Only one serial output @ 1 or 5MHz  Store all channels and BCID for every hit. Depth = 128 bits  Data format : 128(depth)*[2bit*64ch+2 4bit(BCID)+8bit(Header)] = 20kbits  BASICALLY : MAROC with internal RAM and time counting

24 One HaRD_ROC event Discris results – 64*2 bit BCID – 24 bit Chip ID - 8 bit Position Energy Time  160 bits / chip event  Depht is 128

25 Auto trigger and data output Header BCID Ch7 Auto trigger with 10fC: Qinj=10fC in Ch7 DAC0 and DAC1=255 (~5fC)

26 Performance summary Number of inputs/outputs64 inputs, 1 serial output Input Impedance50-70Ω Gain Adjustment0 to 4, 6bits, accuracy 6% Bipolar Fast Shaper≈3.5 mV/fC tp=15ns 10 bit-DAC2.5 mV/fC, INL=0.2% Trigger sensitivityDown to 10fC Slow Shaper (analog readout)≈50 mV/pC, 5fC to 15pC, tp= 50ns to 150ns Analog Xtk2% Analog Readout speed5 MHz Memory depth128 (20kbits) Digital readout speed5MHz or more Power dissipation (not pulsed)100 mW (64 channels)

27 Second generation chip for SiPM : SPIROC SPIROC has been designed to read out the CALICE AHCAL technical prototype

28 Technical prototype architecture  Very similar to SiW ECAL  Following CALICE / EUDET DAQ concept 2.2m ~ 2000 tiles/layer Layer units (assembly) subdivided into smaller PCBs HBUs:Typically 12*12 tiles, 4 ASICs DIF (Layer Concentrator, Clock, control, Configuration) LDA (Module concentrator, Optical link) SPIROC 2 nd gen ASIC incl ADC With 40 µW / ch Temp gradient 0.3 K / 2m From Felix Sefkow’s talk

29 Integrated layer design Sector wall Reflector Foil 100µm Polyimide Foil 100µm PCB 800µm Bolt with inner M3 thread welded to bottom plate MGPD Tile 3mm HBU Interface 500µm gap Bottom Plate 600µm ASIC TQFP-100 1mm high Top Plate 600µm steel Component Area: 900µm high HBU height: 6.1mm (4.9mm without covers => absorber) Absorber Plates (steel) Spacer 1.7mm Top Plate fixing DESY integrated From Felix Sefkow’s talk

30 SPIROC presentation  36-channel readout chip  Self triggered  Energy measurement : 2 gains / 12 bit ADC 1 pe  2000 pe Variable shaping time from 50ns to 100ns pe/noise ratio : 11  Time measurement : 1 TDC (12 bits) step~100 ps – accuracy ~1ns pe/noise ratio on trigger channel : 24 Fast shaper : ~15ns Auto-Trigger on ½ pe  Internal input 8-bit DAC (0-5V) for SiPM gain adjustment It is a System on chip device, including control and communication features

31 Block scheme of SPIROC Bunch crossing Ch. 0 Ch. 1 Analog channel Analog mem. 36-channel 12 bit Wilkinson ADC for charge and time Meas. Analog channel Analog mem. Ch. 35 Analog channel Analog mem. 12-bit counter Time digital mem. Event builder Memory pointer Trigger control Main Memory SRAM Com module HCAL SLAB

32 Time considerations time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 us) Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% duty cycle 199ms (99%)

33 SPIROC running modes Acquisition A/D conversion DAQ When an event occur : Charge is stored in analogue memory Time is stored in digital (coarse) and analogue (fine) memory Trigger is automatically rearmed at next coarse time flag (bunch crossing ID) Depht of memory is 16 The data (charge and time) stored in the analogue memory are sequentially converted in digital and stored in a SRAM. An event in RAM is : The coarse time The fine time The charge The shaper gain The status of the trigger The events stored in the RAM are outputted through a serial link when the chip gets the token allowing the data transmission. When the transmission is done, the token is transferred to the next chip. 256 chips can be read out through one serial link

34 Read out : token ring, zero suppress Acquisition A/D conv.DAQIDLE MODE Chip 0 Chip 1 Acquisition A/D conv.DAQIDLE MODEIDLE Chip 2 Acquisition A/D conv.IDLE MODEIDLE Chip 3 Acquisition A/D conv.IDLE MODEIDLE Chip 4 Acquisition A/D conv.IDLE MODEIDLEDAQ Chip 0Chip 1Chip 2Chip 3Chip 4 5 events3 events 0 event 1 event 0 event Data bus  Read out of millions of channels for ILC

35 SPIROC: One channel schematic

36 DAQ ASIC Chip ID register 8 bits gain Trigger discri Output Wilkinson ADC Discri output gain Trigger discri Output Wilkinson ADC Discri output..… OR36 EndRamp (Discri ADC Wilkinson) 36 TM (Discri trigger) ValGain (low gain or high Gain) ExtSigmaTM (OR36) Channel 1 Channel 0 ValDimGray 12 bits … Acquisition readout Conversion ADC + Writing RAM RAM FlagTDC ValDimGray 12 8 ChipID Hit channel register 16 x 36 x 1 bits TDC ramp StartRampTDC BCID 16 x 8 bits ADC ramp Startrampb (wilkinson ramp) 16 ValidHoldAnalogb RazRangN 16 ReadMesureb Rstb Clk40MHz SlowClock StartAcqt StartConvDAQb StartReadOut NoTrig RamFull TransmitOn OutSerie EndReadOut Chipsat

37 SPIROC : Photoelectron response simulation High gain Preamplifier response Low gain Preamplifier response Fast shaper High gain Slow shaper Low gain Slow shaper Tp=15ns Tp=50ns Noise/pe ratio = 25 Noise/pe ratio = 11 Noise/pe ratio = 3 1mV/pe 10mV/pe 120mV/pe Simulation obtained with SiPM gain = 10 6 _ 1 pe = 160 fC

38 Conclusion  Our group is able to provide in short terms integrated electronic to read out MA-PMT, SiPM or APDs. The versatility of our chips – using programmable parameters (gain, peaking time, thresholds) make them suitable for many applications  Integrated electronic is the best way to read out high number of channels detectors, it allows to reduce cost and improve compacity in every application More information :

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