Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Full Chip Schematic 02/10/2004 Current Stage: Full Chip Schematic 02/10/2004 Design Manager: Rebecca Miller

Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done)  Gate-level design (100% done) This Week NEW Floor Plan NEW Floor Plan Structural Verilog Done Structural Verilog Done  To be done Chip Layout Chip Layout Spice Simulation Spice Simulation Full-chip schematic (transistor-level) Done Full-chip schematic (transistor-level) Done

Design Decisions Chose NAND Decoder for ROMs  NAND Decoder using 2-input predecoders Fast Fast Low power consumption Low power consumption Output inverter to drive Output inverter to drive ~432Tansistors ~432Tansistors  Pseudo-NMOS NOR Decoder Fast Fast Consumes too much power Consumes too much power ~448Transistors ~448Transistors  Pseudo-NMOS NAND Decoder Slow Slow Consumes too much power Consumes too much power

Structural Verilog Structural Verilog

Structural Verilog Testbench Structural Verilog Testbench

Working Structural Verilog – Last Week’s

Revised Floorplan Total Area: um 2 = 0.112mm 2 Transistor Density: trans/ um um PC (wiring) 64 -> 56 64’b 2:1 demux 56’b Key Latch 56’b 2:1 mux KeySub 56’b Register Enc_ShiftL 32’b 2:1 demux 64’b 2:1 mux IP (wiring) Data Reg (L) 32’b IP -1 Wiring Expand 48’b XOR PC-2 wiring 56b -> 48b S-box 512 x 4’b P Wiring 32’b XOR Program Control (Instruction ROM) Input Output Dec_ShiftL Data Reg (R) 32’b 32’b 2:1 mux 415 um

Revised Architecture KeySub 56’b Register 32’b 32’b input Enc_ShiftL Dec_ShiftR IP -1 wiring PC-2 Wiring 56->48 IP wiring Text 64’b Register Expand 32->48 wiring S-Box 512 x 4’b P 32->32 wiring PC (wiring) Key Latch 2:1 mux 2:1 demux R_L Sub_rnd e/d txt_in ready key_in Sh_d Sh_e “R” “L” R L ’b 2:1 56’b 64-> 56 wr_en OUT ready 32 2:1 mux :1 mux Demux

Full-“Chip” Schematic

Top Level “des3”

“Rom Decoder”

“6Bit FA

Barrel Shifter PCROM (InstRom12x54)” Sbox (4x64)” Transistor-Level Schematics

Simulation Result

Updated Transistor Counts and Area

Questions?  Shifting in data using demuxes uses a lot of space  Found methods of doing some permutations with logic Explore/Test Explore/Test