Performed by : Rivka Cohen and Sharon Solomon Instructor : Walter Isaschar המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel Institute of Technology Department of Electrical Engineering Duration : Year Reliable CAN Bus Spring 2004 Characterization Presentation

General Background  Today, many digital systems require high tolerance against failures  Such systems are, for example, satellite control computer and vehicle control system  CAN (Controller Area Network) is a reliable bus protocol and therefore suitable for failure tolerance systems such as the above

Traditional Computer Design The problem : Single damaged component jeopardizes the entire system NOT RELIABLE ! PPC405 OPB Arbiter Memory Controller Memory I/O Custom Logic Fatal Error !

Possible Solutions The Ideal Solution : Connecting all components discretely to each other and to the CPU Complicated, expensive and therefore not practical Major Disadvantages : I/O Memory Custom Logic CPU

Practical Solutions Redundancy CPU I/O Memory Custom Logic Using multiple buses helps recognizing and overcoming bus errors Network topology CPU Memory Custom Logic I/O Router Using network creates several paths between each two devices, which helps error handling

CAN Protocol - Overview  CAN protocol, originally designed for vehicle control system, is now widely used due to its high reliability  Single Channel : the bus consists of a single serial channel that carries bits  Based on four massages types : Data frame, Remote frame, Error frame and Overload frame  Flexible : adding new components is simple  Smart Error Management : faulty components can be recognized and ignored - improves reliability

CAN Protocol Overview ( continued )

Hardware and Software Description  The implementation will be on the programmable device Virtex II Pro by Xilinx which includes a PowerPC processor and FPGA area.  The implementation involves advanced development environment : · Simulation tool (ModelSim) · Synthesis tool (Leonardo) · Place&Route (ISE) · VHDL editor (HDL Designer)

Virtex II Pro Board

Block Diagram OPB to CAN PPC405 OPB Arbiter Memory I/O UART Custom Logic These are all CAN devices !

Block Diagram ( continued ) The problem with CAN protocol : CAN is based on on the ability of multiple devices to drive a value on the same channel simultaneously AND Connecting all devices on the bus thru an AND gate. This allows the devices to “talk” simultaneously on the bus without causing an electrical violation. It is also required to add a read line for each device, because AND gate is not bi-directional Our Solution :

First Semester Timeline Week 1 : Study VHDL and HDL Designer Week 2 : Study Simulation and Synthesis tools Week 3 : Study CAN Protocol specification Week 4 : Study the PPC405 Processor core Week 5 : Study the Virtex II Pro device Week 6 : Program a simple application on Virtex II pro Week 7 : Program an application using the PPC405

First Semester Timeline ( continued ) Weeks 8-10 : Design a small system, containing three devices on one channel, that can “talk” CAN protocol with each other Week 11 : Design the OPB2CAN device, which translates PPC405 PLB protocol to CAN Week : Design a complete CAN based computer by connecting the PPC405 via OPB2CAN to other devices on the CAN channel Week 14 : Final corrections and debugging

3 Second Semester Goals  Examine various bus architectures such as redundancy and network (with routers), as shown in previous slides  Final Goal: Fully operative system, based on CAN Protocol, including simulation of error management and correct operation in case of a faulty device

The End