Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage VI: February 25 h 2004 COMPONENT SIMULATION Presentation #6: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip Integrated Circuit Design Project

Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Gate Level Design  Schematic Design (Fixed)  Input/Output Logic to SBOX Changed and Tested  Top Level Schematic Verified – Pipeline Works!  Layout  Component Layout (Done—Continually Changing)  Simulations (50% Due to Changes in Major Blocks)  To be Done  Optimizations  Everything else… Integrated Circuit Design Project

Design Decisions & Problems DECISIONS Removed XORs from hardcoded values found within: Round Permutation  MixCol  XTime Key Expand Changed ROM to allow for Precharging NMOS Pass-Gates Added to Inputs of ROM: Gate Tied to Clock Added Input and Output Flip-Flops to keep a clean signal PROBLEMS Need to Size Gates More Aggressively ROM DFF XOR (Implemented Using Pass-Transistors!) New Layout of Components Need to Be Finalized—Can’t change them everyday! Integrated Circuit Design Project

ELIMINATION - Eliminate 5 rounds - Eliminate 1 SBOX & control logic - Reduce transistor count to 27k Integrated Circuit Design Project Old Schematic (10 Rounds)

New Schematic (5 Rounds) Mux used in both In and Out logic, moved outside and shared

Verilog Simulation Results e0 34 e7 8b Integrated Circuit Design Project

Schematic Simulation Results Problems! Integrated Circuit Design Project

Schematic Simulation Pipelined! ~One Output Per Clock Cycle~ Integrated Circuit Design Project reg [4:0] counterx; always #5 clk = ~clk; initial begin counterx = 0; end clk) begin counterx = counterx + 1; if (counterx == 21) begin counterx = 0; end end initial begin clk = 1'b1; rst = 1'b1; #10 rst = 1'b0; #10 rst valid_in); text_in1[31:0] = 32'h ; // Expected: 1B3E9EDF key1[31:0] = 32'hFB473859; vin = valid_in); key1[31:0] = 32'b ; text_in1[31:0] = 32'h08f273e6; // Expected: 2DF5C18E vin = valid_in); key1[31:0] = 32'h ; text_in1[31:0] = 32'h10174E72; // Expected: 87FE42E7 vin = valid_in); key1[31:0] = 32'h ; text_in1[31:0] = 32'h30C42168; // Expected: 0BD9AFAC vin = valid_in); key1[31:0] = 32'h2F764A41; text_in1[31:0] = 32'h ; // Expected: 43B28B72 vin = valid_in); key1[31:0] = 32'h ; text_in1[31:0] = 32'h91f0aca1; // Expected: c913f5ed vin = valid_in); key1[31:0] = 32'h851b64d9; text_in1[31:0] = 32'h ; // Expected: 30d0299b vin = valid_in); key1[31:0] = 32'hc ; text_in1[31:0] = 32'h ; // Expected: ec4b0b60 vin = valid_in); key1[31:0] = 32'hfff80000; text_in1[31:0] = 32'h ; // Expected: b3adb97e vin = valid_in); key1[31:0] = 32'h ; text_in1[31:0] = 32'h9b0cb284; // Expected: 69551ee1 vin = 1; #10000 $finish; end

Old Floorplan Integrated Circuit Design Project ROM and Control Key Expand no pipe In Logic & Out Logic Round Permutations Key Expand Text & Key Output 345 um x 325 um

Updated Floorplan 325 um x 330 um Metal 3 Metal 2 Metal 1 Metal 4 SBOX and Control Logic Text DFFs and Add Round Key 5 th Round Key Expand Input to SBOX Logic & Select Output and Input Logic 4 Rounds of Key Expand 4 Rounds of Round Permutation Input/Output Logic CLK Divider Select & Input Logic SBOX and Control Logic Final Text Out Key DFFs and Input Logic

Updated Floorplan 325 um x 330 um Key[32] Text[32] Metal 3 Metal 2

Updated Floorplan 325 um x 330 um Key[32] Text[32] Metal 3 Metal 2 Multiple Metal 4 Direction (Where Things Have Already Been Wired Up – No Global Routing)

Updated Floorplan 325 um x 330 um Key[32] Text[32] Metal 3 Metal 2 Multiple Metal 4 Direction (Where Things Have Already Been Wired Up – No Global Routing) Output

ROM Schematic Integrated Circuit Design Project

ROM Control with PMOS Integrated Circuit Design Project

Old ROM and Control Logic Integrated Circuit Design Project ROM Control Logic

New ROM and Control Logic (New Row of NMOS: Gates Tied to Clock to Control Inputs—Allows Precharging) Integrated Circuit Design Project ROM Control Logic

Round Permutation Integrated Circuit Design Project

Old Round Permutation Integrated Circuit Design Project

Updated: Round Permutation Integrated Circuit Design Project DFFsXORs Inputs

Key Expand Integrated Circuit Design Project

Key Expand Layout (Will Be Changed) Integrated Circuit Design Project Inputs (M2 Down, M3 Across) Outputs (M4) DFFs 1 st Level XORs

SBox Mux Tree In-Logic Integrated Circuit Design Project 8 x Mux5 Previous Logic To ROM

SBOX Select Tree In-Logic Integrated Circuit Design Project Current Logic

SBOX Select Tree In-Logic Integrated Circuit Design Project Current Logic Tree Structure Difficult to Implement in Layout Needed to finalize wiring from other modules in order to be more efficient in arranging in-logic Now: Decided to put next to its corresponding stage

SBox Mux Tree In-Logic Integrated Circuit Design Project Current Logic

SBox Mux Tree Out-Logic Integrated Circuit Design Project

Changes To… XTime (Found in MixCol of RoundPermutations) Integrated Circuit Design Project

Changes To… XTime (Found in MixCol of RoundPermutations) Integrated Circuit Design Project 5XORs * 2 XTime per MixCol * 2 MixCol Per Round * 4 Rounds = 80 XORs

Changes To… KeyExpand (The Hardcoded RCON Value) Integrated Circuit Design Project

Changes To… KeyExpand (The Hardcoded RCON Value) One Row of XORs Eliminated Integrated Circuit Design Project 16 XORs per KeyExpand * 5 KeyExpands = 80 XORs

Waves D-FlipFlop Layout Integrated Circuit Design Project

Waves D-FlipFlop Propagation Time Integrated Circuit Design Project ps

Waves D-FlipFlop Rise Time Integrated Circuit Design Project ns

Waves D-FlipFlop Fall Time Integrated Circuit Design Project ns

Waves XOR Propagation Time Integrated Circuit Design Project ps

Waves XOR Rise Time Integrated Circuit Design Project ps

Waves XOR Fall Time Integrated Circuit Design Project ps

Waves 4-XOR Propagation Time Integrated Circuit Design Project ps

Waves ROM Propagation Time Integrated Circuit Design Project ps

Waves ROM Control Propagation Time Integrated Circuit Design Project ps

Waves ROM Control Fall Time Integrated Circuit Design Project ps

Waves Longest Logic Path (Not Including ROM) Integrated Circuit Design Project ps

Current Speed Estimation 200 MHz Integrated Circuit Design Project

COMPONENTS AREA ESTIMATE ( um 2 ) Key Schedule  Registers & XORs 80 um x 40 um x 4 um + 35 um x40 um = 14,200 um 2 ROM  SBOX and Control Logic (2) 60 um x 250 um x 2 = 30,000 um 2 Transformation  Register & XORs 70 um x 70 x 4 = 19,600 um 2 Add Round Key & Final Text Out 70 um x 15 um x 2 = 2100 um 2 Others  Buffers & Wiring 10% = 6,590 um 2 CURRENT AREA DIMENSIONS Total: 330 um x 325 um (taken from current floorplan)

Current Transistor Count with 5 Rounds of Encryption (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (5) 136  SBoxMuxTreeIn (Text) 2336  SBoxMuxTreeIn (Key) 1056  SBoxMuxTreeOut (Text) 3992  SBoxMuxTreeOut (Key) 2038  ROM with New Control Logic (3) 7332  Key Expansion (5) 1920  Round Permutation (4) 5312  Final Text Out 256 Total: Total with Buffer Estimate (10%) New Total: (From LVS) 25, Integrated Circuit Design Project

Questions?