FPGA chips and DSP Algorithms By Emily Fabes

2 Agenda FPGA Background Reasons to use FPGA’s Advantages and disadvantages of using FPGA’s Sample VHDL code Questions

3 FPGA Background Information Field Programmable Gate Arrays Made up of Logic Blocks, I/O Blocks and Programmable Interconnect

4 Programming FPGA’s Method #1 – Using a hardware description language (e.g.. VHDL)  High level design for FPGA’s  Routing and wiring done automatically Method #2 – Using placing components manually using a schematic drawing tool  Low level design for FPGA’s

5 Circuit Implementation Combinational Logic  No dependence on previous input values Ex. AND gate, OR gate, NOT gate Sequential Logic  Has dependence on previous input values  Contains a flip-flop, which give “memory” to the circuit

6 Why Use FPGA’s? High performance circuits previously implemented on ASIC’s  ASIC – Application Specific Integrated Circuit  ASIC’s have long design process FPGA’s only recently became large enough to implement these applications FPGA’s have become cheaper

7 Why Use FPGA’s? Better design tools have been made for circuit creation Can upgrade the design later by reprogramming or upgrading the chip New FPGA’s now offer hardwired multipliers throughout the chip  Makes multiply and accumulate easier and faster

8 Advantage – Flexibility Can designate more hardware to make a section faster Can the chip use in different applications Code blocks are reusable after they have been optimized

9 Advantage – Precision Precision can easily be added to any point in a circuit Example VHDL code  signal u_k : std_logic_vector(15 downto 0);  signal u_k_3 : std_logic_vector(17 downto 0); Disadvantage – takes up resources

10 Advantage – Shifting Shifting by multiples of two is easy and efficient Virtually no hardware cost, just wiring Can implement multiplies as combinations of shifts and adds  3 =

11 Disadvantage – Designers Cannot just switch a DSP designer from a SHARC to a FPGA Different style of thinking required  VHDL code is not like C even though it might look like C  VHDL creates circuits  Cannot just step through the code, parallel circuits running

12 Disadvantage – Timing Make sure that when using sequential circuits that data is valid when you need it Routing delays

13 Disadvantage – Optimization Optimization is very hard  Must really understand what is going on and how this affects the timing of the circuit Not so much code optimization as hardware optimization

14 VHDL Code Example

15 Covered FPGA Background Reasons to use FPGA’s Advantages and disadvantages of using FPGA’s Sample VHDL code

16 References FPGA/DSP blend tackles telecom apps Jennifer Eyre, Senior DSP Analyst, Berkeley Design Technology Inc., Berkeley, Calif. Reduce Build Costs by Offloading DSP Functions to an FPGA Digital Design Principles and Practices by J Wakerly ENEL 527 Lab 3

17 Questions?