1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
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1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2
1/31/20082 Circuits are permanent They perform one function or set of functions Once manufactured, they cannot be changed Constrained to parts Need to stock many different parts Most resources (power, board area, manufacturing cost) are consumed by the “package” but not by the “silicon”, which performs the actual computation. Automation is impossible Example Fixed Logic Devices (e.g. SSI/MSI) Small-Scale Integration (SSI) uses circuits containing transistors numbering in the tens, while Medium-Scale Integration" (MSI) contains hundreds of transistors on each chip. Disadvantages
1/31/20083 Devices can be changed at any time to perform any number of functions. Use a single chip (or a small number of chips). Program it for the circuit you want. Testing using simulation. Then, a design can be quickly programmed into a device, and immediately tested in a live circuit. Programmable Logic Devices Lecture Notes – Lab 2 Example: Field programmable gate array (FPGA) A gate-array-like architecture with a matrix of logic cells surrounded by a periphery of I/O cells where the interconnect mask is defined after the IC has been manufactured.
1/31/20084 Lecture Notes – Lab 2 FPGA. Basic idea: two-dimensional array of configurable logic blocks (CLBs) that can implement combinational or sequential logic Simplified version of FPGA internal architecture FPGAs provides a method to configure (program): 1. The interconnection between CLBs. 2. The function of each CLB.
1/31/20085 Lecture Notes – Lab 2 FPGA Generic Design Flow Design Entry Design Verification Design Implementation Design Entry: Create your design files using: schematic editor or hardware description language (e.g., VHDL) Design “implementation” on FPGA: Partition, place, route, … Design verification: Use Simulator to check function, Load onto FPGA device (cable connects PC to development board) check operation at full speed in real environment.
1/31/20086 Lecture Notes – Lab 2 Programming Language Can we use a traditional programming language (e.g., C or Java) as a Hardware description language (HDL)? Traditional PL Useful to model sequential processes – Operations performed in a sequential order – Help human's thinking process to develop an algorithm step by step – Resemble the operation of a basic computer model
1/31/20087 Lecture Notes – Lab 2 Digital systems Digital systems are about signals and their values Events, propagation delays, concurrency. Signal value changes at specific points in time. Time ordered sequence of events produces a waveform These characteristics are hard to be captured by traditional PLs
1/31/20088 Key Point: You can use the software to describe the behavior of the circuit you wish to develop and then implement the design on programmable logic devices. VHDL - Very High Speed Integrated Circuit Hardware Description Language Lecture Notes – Lab 2
1/31/20089 Describing the Interface: The Entity Construct The interface is a collection of ports –Ports are a new programming object: signal –Ports have a type, e.g., bit –Ports have a mode: in, out, inout (bidirectional) entity half_ADder is port ( a, b : in bit; sum, carry :out bit); end entity half_adder; case insensitive VHDL 1993 b a sum carry
1/31/200810 The Signal Object Type VHDL supports four basic objects: variables, constants, signals and file types (1993) Variable and constant types –Follow traditional concepts The signal object type is motivated by digital system modeling –Distinct from variable types in the association of time with values –Implementation of a signal is a sequence of time-value pairs! –Analogous to wires used to connect components of a digital circuit SIGNAL sig1: STD_LOGIC; SIGNAL sig1: STD_LOGIC := ‘1’; SIGNAL sig1(1 DOWNTO 0): STD_LOGIC_VECTOR := “10”; Signal declaration Signal signal_name: signal_type := initial_value
1/31/200811 Describing Behavior: The Architecture Construct Description of events on output signals in terms of events on input signals: the signal assignment statement Specification of propagation delays b a sum carry entity half_adder is port (a, b : in bit; sum, carry :out bit); end entity half_adder; architecture behavioral of half_adder is begin sum <= (a xor b) after 5 ns; carry <= (a and b) after 5 ns; end architecture behavior; VHDL 1993
1/31/200812 Basic VHDL building blocks Lecture Notes – Lab 2 Example 1: Consider the following circuit: Entity ENTITY fewgates IS PORT ( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Y : OUT STD_LOGIC ); END fewgates; ARCHITECTURE c1_behavior OF fewgates IS SIGNAL sig1: STD_LOGIC; BEGIN sig1 <= (NOT A) AND (NOT B); Y <= C OR sig1; END c1_behavior; Architecture sig1
1/31/200813 Signal Assignment The constant programming object –Values cannot be changed Use of signals in the architecture –Internal signals connect components A statement is executed when an event takes place on a signal in the RHS of an expression –1-1 correspondence between signal assignment statements and signals in the circuit –Order of statement execution follows propagation of events in the circuit –Textual order does not imply execution order