1. EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Combinational Circuits

2. Overview Combinational Circuit Combinational Circuit Chip Design styles Chip Design styles Full-custom design Full-custom design Cell library based design Cell library based design Programmable Logic Array Programmable Logic Array 2015/12/21 PJF- 2Combinational Logic

3. 2015/12/21 PJF- 3Combinational Logic Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables, there are 2 n possible binary input combinations. For n input variables, there are 2 n possible binary input combinations. For each binary combination of the input variables, there is one possible output. For each binary combination of the input variables, there is one possible output.

4. 2015/12/21 PJF- 4Combinational Logic Combinational Circuits (cont.) Hence, a combinational circuit can be described by: Hence, a combinational circuit can be described by: 1. A truth table that lists the output values for each combination of the input variables, or 2. m Boolean functions, one for each output variable. Combinational Circuit n-inputsm-outputs

5. 2015/12/21 PJF- 5Combinational Logic Combinational vs. Sequential Circuits Combinational circuits are memory-less. Thus, the output value depends ONLY on the current input values. Combinational circuits are memory-less. Thus, the output value depends ONLY on the current input values. Sequential circuits consist of combinational logic as well as memory elements (used to store certain circuit states). Outputs depend on BOTH current input values and previous input values (kept in the storage elements). Sequential circuits consist of combinational logic as well as memory elements (used to store certain circuit states). Outputs depend on BOTH current input values and previous input values (kept in the storage elements).

6. 2015/12/21 PJF- 6Combinational Logic Combinational vs. Sequential Circuits Combinational Circuit n-inputsm-outputs (Depend only on inputs) Combinational Circuit n-inputsm-outputs Storage Elements Next state Present state Sequential Circuit Combinational Circuit

7. 2015/12/21 PJF- 7Combinational Logic Important Design Concepts Modern digital design deals with various methods and tools that are used to design and verify complex circuits and systems. Modern digital design deals with various methods and tools that are used to design and verify complex circuits and systems. Concepts: Concepts: Design Hierarchy Design Hierarchy Computer-Aided-Design (CAD) tools Computer-Aided-Design (CAD) tools Hardware Description Languages (HDLs) Hardware Description Languages (HDLs)

8. 2015/12/21 PJF- 8Combinational Logic Design Hierarchy “Divide-and-Conquer” approach used to cope with the challenges of designing complex circuits and systems (many times in the order of millions of gates). “Divide-and-Conquer” approach used to cope with the challenges of designing complex circuits and systems (many times in the order of millions of gates). Circuit is broken into blocks, repetitively. Circuit is broken into blocks, repetitively.

9. 2015/12/21 PJF- 9Combinational Logic Design Hierarchy Example: 9-input odd function (for counting # of 1 in inputs)

10. 2015/12/21 PJF- 10Combinational Logic Why is Hierarchy useful? Reduces the complexity required to design and represent the overall schematic of the circuit. Reduces the complexity required to design and represent the overall schematic of the circuit. Reuse of blocks is possible. Identical blocks can be used in various places in a design, or in different designs. Reuse of blocks is possible. Identical blocks can be used in various places in a design, or in different designs.

11. 2015/12/21 PJF- 11Combinational Logic Reusable Functions and CAD Whenever possible, we try to decompose a complex design into common, reusable function blocks Whenever possible, we try to decompose a complex design into common, reusable function blocks These blocks are These blocks are verified and well-documented verified and well-documented placed in libraries for future use placed in libraries for future use

12. 2015/12/21 PJF- 12Combinational Logic Integrated Circuits Integrated circuit (a chip) is a semiconductor crystal (most often silicon) containing the electronic components for the digital gates and storage elements which are interconnected on the chip. Integrated circuit (a chip) is a semiconductor crystal (most often silicon) containing the electronic components for the digital gates and storage elements which are interconnected on the chip. Terminology - Levels of chip integration Terminology - Levels of chip integration SSI (small-scale integrated) - fewer than 10 gates SSI (small-scale integrated) - fewer than 10 gates MSI (medium-scale integrated) - 10 to 100 gates MSI (medium-scale integrated) - 10 to 100 gates LSI (large-scale integrated) - 100 to thousands of gates LSI (large-scale integrated) - 100 to thousands of gates VLSI (very large-scale integrated) - thousands to 100s of millions of gates VLSI (very large-scale integrated) - thousands to 100s of millions of gates

13. 2015/12/21 PJF- 13Combinational Logic Technology Parameters Specific gate implementation technologies are characterized by the following parameters: Specific gate implementation technologies are characterized by the following parameters: Fan-in – the number of inputs available on a gate Fan-in – the number of inputs available on a gate Fan-out – the number of standard loads driven by a gate output Fan-out – the number of standard loads driven by a gate output Cost for a gate - a measure of the contribution by the gate to the cost of the integrated circuit Cost for a gate - a measure of the contribution by the gate to the cost of the integrated circuit Propagation Delay – The time required for a change in the value of a signal to propagate from an input to an output Propagation Delay – The time required for a change in the value of a signal to propagate from an input to an output Power Dissipation – the amount of power drawn from the power supply and consumed by the gate Power Dissipation – the amount of power drawn from the power supply and consumed by the gate

14. 2015/12/21 PJF- 14Combinational Logic Propagation Delay Propagation delay is the time for a change on an input of a gate to propagate to the output. Propagation delay is the time for a change on an input of a gate to propagate to the output. Delay is usually measured at the 50% point with respect to the H and L output voltage levels. Delay is usually measured at the 50% point with respect to the H and L output voltage levels. High-to-low falling and low-to-high rising delays. High-to-low falling and low-to-high rising delays.

15. 2015/12/21 PJF- 15Combinational Logic Propagation Delay Example IN (volts) OUT (volts) t (ns) 1.0 ns per division

16. 2015/12/21 PJF- 16Combinational Logic Chip Design Styles Full custom - the entire design of the chip down to the smallest detail of the layout is performed Full custom - the entire design of the chip down to the smallest detail of the layout is performed Expensive, its timing and power is hard to analyze Expensive, its timing and power is hard to analyze only for dense, fast chips with high sales volume only for dense, fast chips with high sales volume Standard cell - blocks have been design ahead of time or as part of previous designs Standard cell - blocks have been design ahead of time or as part of previous designs Intermediate cost Intermediate cost Less density and speed compared to full custom Less density and speed compared to full custom Gate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections between gates are specific to a design Gate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections between gates are specific to a design Lowest cost Lowest cost Less density compared to full custom and standard cell Less density compared to full custom and standard cell Prototype design Prototype design The base of FPGA The base of FPGA

17. 2015/12/21 PJF- 17Combinational Logic Cell Libraries Cell - a pre-designed primitive block Cell - a pre-designed primitive block Cell library - a collection of cells available for design using a particular implementation technology Cell library - a collection of cells available for design using a particular implementation technology Cell characterization - a detailed specification of a cell for use by a designer Cell characterization - a detailed specification of a cell for use by a designer

18. 2015/12/21 PJF- 18Combinational Logic Cell Library Based Design Procedure 1. Specification Write a specification for the circuit if one is not already available Write a specification for the circuit if one is not already available 2. Formulation Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification 3. Optimization Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters

19. 2015/12/21 PJF- 19Combinational Logic Cell Library Based Design Procedure 4. Technology Mapping Map the logic diagram to the implementation technology selected Map the logic diagram to the implementation technology selected Map to CMOS Map to CMOS 5. Evaluation Evaluate the timing and power Evaluate the timing and power

20. 2015/12/21 PJF- 20Combinational Logic Design Example 1. Specification BCD to Excess-3 code converter BCD to Excess-3 code converter Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word

21. 2015/12/21 PJF- 21Combinational Logic Design Example (continued) 2. Formulation Conversion of 4-bit codes can be most easily formulated by a truth table Conversion of 4-bit codes can be most easily formulated by a truth table Variables - BCD: A,B,C,D Variables - BCD: A,B,C,D Variables - Excess-3 W,X,Y,Z Variables - Excess-3 W,X,Y,Z Don’t Cares - BCD 1010 to 1111 Don’t Cares - BCD 1010 to 1111 Input BCD A B C D Output Excess-3 WXYZ 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 1

22. 2015/12/21 PJF- 22Combinational Logic Design Example (continued) 3. Optimization a. K-maps W = A + BC + BD X = C + D + B Y = CD + Z = BCD B C D D

23. 2015/12/21 PJF- 23Combinational Logic Design Example (continued) 3. Optimization (continued) Multiple-level using transformations W = A + BC + BD X = C + D + B Y = CD + Z = Multiple-level using transformations W = A + BC + BD X = C + D + B Y = CD + Z = Perform extraction, finding factor: Perform extraction, finding factor: T 1 = C + D W = A + BT 1 X = T 1 + B Y = CD + Z = T 1 = C + D W = A + BT 1 X = T 1 + B Y = CD + Z = B C DB C D D B CD CD D

24. 2015/12/21 Combinational Logic Design Example (continued) 4. Technology Mapping Map with a library containing inverters and 2-input NAND, and then map it to a CMOS based circuit Map with a library containing inverters and 2-input NAND, and then map it to a CMOS based circuit Z A B C D W X Y Z

25. 2015/12/21 PJF- 25Combinational Logic NAND Mapping Example

26. Timing Analysis Use static timing analysis which has been covered. Use static timing analysis which has been covered. 2015/12/21 PJF- 26Combinational Logic

27. 21-Dec-15 PJF - 27Combinational Logic Programmable Logic Array The set of functions to be implemented is first transformed to product terms The set of functions to be implemented is first transformed to product terms Since output inversion is available, terms can implement either a function or its complement Since output inversion is available, terms can implement either a function or its complement

28. 21-Dec-15 PJF - 28Combinational Logic Programmable Logic Array Example To implement To implement F1= A’B’C+A’BC’+AB’C’=(AB+AC+BC+A’B’C’)’ F1= A’B’C+A’BC’+AB’C’=(AB+AC+BC+A’B’C’)’ F2=AB+AC+BC F2=AB+AC+BC

29. 21-Dec-15 PJF - 29Combinational Logic Programmable Logic Array Example XFuse intact Fuse blown 0 1 F 1 F 2 A B C CBACBA 1 2 4 3 X X XX X X X X X X X X X X X X X X