1 4-bit ALU Cailan Shen Ting-Lu Yang Advisor: Dr. Parent May 11, 2005.

Slides:



Advertisements
Similar presentations
ALU Organization Michael Vong Louis Young Rongli Zhu Dan.
Advertisements

1 Specifications Functionality: AND, OR, XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 µm ×400µm Prepared by: Christie Ma, Manjul.
ES 112 Project 2 bit ALU.
1 8-Bit Barrel Shifter Cyrus Thomas Ekemini Essien Kuang-Wai (Kenneth) Tseng Advisor: Dr. David Parent December 8, 2004.
1 Improvement of Si solar sell performance by adding an anti- reflective coating (ARC) Your name goes here. Advisor: Dave Parent Co-Advisor: Lily He 14.
1 4-BIT ARITHMETIC LOGIC UNIT MOTOROLA SN54/74LS181 Arora Shalini Guttal Pratibha Modgi Chaitali Shanmugam Ramya Advisor: Dave Parent Date:
1 8-bit X 8-bit SRAM and 3 X 8 Decoder Irina Vazir, Prabhjot Balaggan and Sumandeep Kaur Advisor: Dr. David Parent December 06, 2004.
Random Number Generator Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan.
1 Hamming Code Clarissa David Timmy Lau WingChing Lin Jonathan Lee Advisor: Dr. David Parent December 7, 2005.
1 Serial Multiplier Ann Zhou Ying Yan Wei Liang Advisor: David Parent May 17 th, 2004.
1 Encoding Logic for 5 bit Analog to Digital Converter By:Kaneez Fatimah Ranjini Bhagavan Padmavathy Desikachari Veena Jain Advisor: Dr. David Parent Date:
6-BIT THERMOMETER CODER
1 4 - Bit Arithmetic Logic Unit 74HC/HCT181 Aruna Ketaraju Sowmya Paramkusam Balakrishna Peddireddi Advisor: Dave Parent 12/06/2004.
1 4-bit Decimation Filter Rashmi Joshi Siu Kuen(Steve) Leung Cuong Trinh Advisor: Dr. David Parent December 5, 2005.
1 Modular Arithmetic Logic Unit By Salvador Sandoval & Lucas Morales Advisor: Dave Parent December 6, 2004.
1 16 BIT KOGGE-STONE TREE ADDER Shayan Kazemkhani Nghia Do Jia Kang Yu Toan Luong Advisor: David Parent May 8 th 2006.
San Jose State University Department of Electrical Engineering Dec 5th, Fall 2005 EE 166 PROJECT Advisor: Prof. David Parent Group Members Radhika Arora,
1 Hamming Code Clarissa David Timmy Lau WingChing Lin Jonathan Lee Advisor: Dr. David Parent December 5, 2005.
1 4-BIT ARITHMETIC LOGIC UNIT Motorola MC54/74F181 Heungyoun Kim Lu Gao Jun Li Advisor: Dr. David W. Parent DATE: 12/05/2005.
1 Simple FPGA David, Ronald and Sudha Advisor: Dave Parent 12/05/2005.
4-bit Grey Code Converter with Counter Lincoln Chin Dat Tran Thao Nguyen Tien Huynh.
1 Design of 4- BIT ALU Swetha Challawar Anupama Bhat Leena Kulkarni Satya Kattamuri Advisor: Dr.David Parent 05/11/2005.
1 Design of 8- Bit ALU Neelam Chaudhari Archana Mulukutla Namita Mittal Madhumita Sanyal Advisor : Dr. David Parent Date : May 8, 2006.
1 ACS Unit of Viterbi Decoder Audy,Garrick Ng, Ichang Wu, Wen-Jiun Yong Advisor: Dave Parent Spring 2005.
1 DESIGN OF 4-BIT ALU Fairchild Semiconductor DM74LS181 Prashanth Kommuri Akram Khan Gopinath Akkinepally Advisor: Dr. David W. Parent 5 December 2005.
1 4 Bit ALU with Carry Look Ahead Generator Piyu Singh Dhaker Kedar Bhatawadekar Nikhat Baig Advisor: Dave Parent DATE:12/05/05.
1 64-Bit AND Gate Phong Nguyen Steve Turner Harpreet Dhillon Mahrang Saeed Advisor: Dave Parent 5/8/06.
1 Serial Decoder & Multiplexer Ryan Bruno Gly Cruz Frank Gurtovoy Christopher Plowman Advisor: Dr. David Parent May 11 (or 16), 2005.
1 5-bit Flash Encoder Nam Van Do, Dave Flores, Shawn Smith Advisor: Dr. David Parent December 6, 2004.
1 8-Bit Binary-to-Gray Code Converter Mike Wong Scott Echols Advisor: Dave Parent May 11, 2005.
SADDAPALLI RUDRA ABHISHEK
Advisor: Prof. David W. Parent Presentation Date: 12/05/05
4-bit ALU Yamei Li, Yuping Liang Hua Qu, James Hsu
1 8-Bit Comb Filter Shweta Agarwal, Kevin Federico, Chad Schrader, Jing Liu Advisor: Professor David Parent Date: May 11, 2005.
1 4-Bit ALU Chun-Wai Lee Shiela Valenciano Advisor: Dr. David Parent 12/05/05.
1 Design of 4-bit ALU Swathi Dasoju Mahitha Venigalla Advisor: David W.Parent 6 th December 2004.
1 8 Bit Gray Code Converter Rasha Shaba Hala Shaba Kai Homidi Advisor: David Parent DATE 12/06/04.
1 DESIGN OF 8-BIT ALU Vijigish Lella Harish Gogineni Bangar Raju Singaraju Advisor: Dr. David W. Parent 8 May 2006.
CSCE 613 VLSI design is mostly about CAD/EDA tools Many different tools for VLSI design Developed as a new course, independent of previous version Adopt.
1 4 BIT Arithmetic Logic Unit (ALU) Branson Ngo Vincent Lam Mili Daftary Bhavin Khatri Advisor: Dave Parent DATE: 05/17/04.
4 Bit Arithmetic Logic Unit Presented by Ipsita Praharaj, Shalaka Ghawate Advisor: Dr. David Parent Date:05/11/04.
Random Number Generator Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan.
4 Bit ALU Geeping (Frank) Liu, Kasem Tantanasiriwong,
1 5 bit binary to 1 of 32 select decoder (to be used in 5 bit DAC) Dan Brisco, Steve Corriveau Advisor: Dave Parent 14 May 2004.
1 8 Bit ALU EE 166 Design Project San Jose State University Roger Flores Brian Silva Chris Tran Harizo Yawary Advisor: Dr. Parent May 2006.
1 ACS Unit for a Viterbi Decoder Garrick Ng, Audelio Serrato, Ichang Wu, Wen-Jiun Yong Advisor: Professor David Parent EE166, Spring 2005.
1 5-bit Decimation Filter Loretta Chui, Xiao Zhuang Hock Cheah, Gita Kazemi Advisor: David Parent December 6, 2004.
1 8 Bit ALU Rahul Vyas Gyanesh Chhipa Jaimin Shah Advisor: Dr. David W. Parent 05/08/2006.
1 4 BIT Arithmatic and Logic Unit (Fairchild DM74LS181) Kunjal Shah Radha Dharmana Rutu Pandya Vennela Patchala. Advisor: Dr. David, Parent December 5,
1 Error Detecting Adder Yugandhar Asmath Saikiran Vodela Pavan Polum Puneet Shrivastava Advisor: Dr. David W Parent 8 th May 2006.
4 BIT Arithmetic And Logic Unit (ALU) Philips 74HC/HCT181 Brijesh Chavda Meet Aghera Mrugesh Chandarana Sandip Patel Adviser David Parent Date: 12/03/05.
1 4 Bit Arithmetic Logic Unit Adithya V Kodati Hayagreev Pattabhiraman Vemuri Koneswara Advisor: Dave Parent 12/4/2005.
1 Four-Bit Serial Adder By Huong Ho, Long Nguyen, Lin-Kai Yang Ins: Dr. David Parent Date: May 17 th, 2004.
Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.
Project submitted By RAMANA K VINJAMURI VLSI DESIGN ECE 8460 Spring 2003.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Final project Speaker:Aeag ( 柯鴻洋 ) Advisor: Prof. Andy Wu 2003/05/29.
Design of 4-bit ALU.
16 Bit Logarithmic Converter Tinghao Liang and Sara Nadeau.
Gates AND, OR, NOT NAND, NOR Combinational logic No memory A set of inputs uniquely and unambiguously specifies.
Written by Whitney J. Wadlow
VLSI 1 382M/460R Lab 2 DESIGN OF AN ARITHMETIC LOGIC UNIT (ALU)
Combinational Circuits
4 BIT Arithmetic Logic Unit (ALU)
Digital Decode & Correction Logic
ECE 3130 – Digital Electronics and Design
Design of an 8 Bit Barrel Shifter
Design of an Arithmetic Logic Unit (ALU)
Combinational Circuits
Design of Digital Circuits Lab 5 Supplement: Implementing an ALU
Advisor: Jin-Fu Li TA: Shin-Yo Lin
Presentation transcript:

1 4-bit ALU Cailan Shen Ting-Lu Yang Advisor: Dr. Parent May 11, 2005

2 Agenda Introduction Project (Experimental) Details –ALU design in Cadence –DFF, MUX and Adder Summary –Project result –Lesson learned

3 Introduction The 4-bit ALU that our group designed can perform following functions: –Add, Subtract, NOR, OR, and AND. The 4-bit ALU operates at 200 MHz with an area of 300 um x 320 um and use 1.3 mW power. The 4-bit ALU is made up of 4 identical 1-bit ALU, and DFFs ensure the 4-bit ALU to obtain the correct inputs and send out correct outputs. This project is worthwhile because this ALU has all the logic blocks that we learned in class.

4 Project Description and ALU Schematic -1-bit Adder -Four 2 to 1 MUXs -1 AND and 1 OR gates -Four control inputs, two data inputs.

5 Longest Path Calculations Note: All widths are in microns and capacitances in fF

6 4-bit ALU Layout and LVS

7 Simulation ALU Control LinesFunction A_invB_invOP1OP0 0000AND 0001OR 0010ADD 0110SUBTRACT 1100NOR Inputs AB A – B = =1111 Cout = 0 (Borrowed)

8 Verification of Final Output

9 Power = 1.3 mW

10 Summary After this project, we became familiar with Cadence tool and the fundamental concepts of IC design. The total area is = 300um x 320um The power = 1.3mW Lessons learned How to fix the LVS error Learn how to work in a team Learn how to make trade offs

11 Acknowledgements Thanks to Cadence Design Systems for the VLSI lab Thanks to Synopsys for Software donation. Thanks to Professor David Parent.