1. 1 4-Bit ALU Chun-Wai Lee Shiela Valenciano Advisor: Dr. David Parent 12/05/05

2. 2Agenda Abstract Introduction  Why  Background information Project Summary Project Details Results  Schematics  LVS Reports  Layouts  Simulations Summary

3. 3 Abstract The design consists of a 4-bit Arithmetic Logic Unit (ALU) that contains: AND2, OR2, XOR, Full ADDER, DFF Design Area = 283.8 x 325.6 μm 2 Maximum Power = 30 mW

4. 4 Introduction An ALU is the high-speed CPU circuit that performs calculations and comparisons This project illustrates the design and functions of an ALU

5. 5 Introduction The design consists of an ALU that manipulates two 4-bit inputs. These inputs produce an output that corresponds to the output selector line Sel1Sel2Output 00AND 01OR 10XOR 11ADDER The table displays the possible outputs

6. 6 Project Summary The project design utilizes parallel computing so that the clock resources are used efficiently AND, OR, XOR, and ADDER that are cascade together generate outputs in parallel at the MUX input

7. 7 Longest Path Calculations Note: All widths are in microns and capacitances in fF T paveCgWn ( X 10^-4)Wp ( X 10^-4)New Cg 1DFF 2INV0.5ns30ff1.52.556.91ff 3AOI Mux0.5ns7ff1.83.098.33ff 4INV0.5ns8ff1.52.557ff 5INV0.5ns7ff1.52.557ff 6AOI0.5ns7ff1.52.557ff 7INV0.5ns7ff1.52.557ff 8AOI0.5ns7ff1.52.557ff 9INV0.5ns7ff1.52.557ff 10DFF

8. 8 D Flip Flop - Schematic

9. 9 D Flip Flop – Layout, LVS

10. 10 DFF Rise and Fall Time Setup Rise Time = 1.15ns Setup Fall Time = 0.71 ns Hold Rise and Fall Time

11. 11Schematic

12. 12 ALU - Layout

13. 13 Verification (LVS for ALU)

14. 14 Transient Delay and Power

15. 15 Cost Analysis Time spent on each stage of the project  Designing logic: 1 week  Verifying logic: 1 week  Verifying timing: 2 weeks  Layout: 3 weeks  Post extracted timing: 3 days

16. 16 Lessons Learned How to use Cadence tool How to design an integrated circuit How to apply knowledge learned in class into lab work How to construct an efficient design How to fix LVS errors Work on the lab early in the morning!!!

17. 17 Summary The project is an application of the knowledge learned in class through circuit testing and design Designed a 4-Bit ALU at 200MHz frequency with setup and hold time at1ns, driving up to 30fF This circuit can be used as a building block for 16/32-bit ALU The Logic design can be modified to perform more functions Design Area = 284 x 325 μm 2 Maximum Power = 30 mW

18. 18 Acknowledgements Thanks to Professor David W. Parent for his guidance. Thanks to Cadence Design Systems for the VLSI lab Thanks to the help from EE166 classmates