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Combinational Circuits

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Presentation on theme: "Combinational Circuits"— Presentation transcript:

1 Combinational Circuits

2 Decoder Decoder : Takes n inputs Selects one of 2n output lines

3 Truth Table Expression for each output has one term
O0 = I1' I0' O1 = I1 I0' O2 = I1' I0 O3 = I1 I0

4 Decoder Implementation O0 = I1' I0' O1 = I1 I0' O2 = I1' I0 O3 = I1 I0

5 Sample Use 3  8 decoder used to pick instruction

6 Multiplexer Multiplexer : 2 input multiplexer 4 input multiplexer
N data lines lines Log2(N) select lines 2 input multiplexer 4 input multiplexer

7 Decode to Mux Multiplexer selection logic = decoder
4 input multiplexer

8 Shifter 1 bit shifter D4 goes to either S3 or S5

9 Shifter 1 bit shifter If C = 1, goes to S5

10 Shifter 1 bit shifter If C = 0, goes to S3

11 Shifter S = direction 0: left, 1: right Logical shift:
Left bit always 0 on right shift

12 Multibit Shift 4 bit wide 0-3bit shift S selects direction
Multiplexers select correct pattern

13 Half Adder Half Adder : adds A + B, produce sum + carry 1 1 1

14 Half Adder Truth Table Inputs a & b Carry : c Sum : s

15 First Pass

16 XOR Function XOR gate : exclusive OR Notation: A  B OR A ^ B
AB' + A'B Notation: A  B OR A ^ B

17 Using XOR Half Adder Final

18 Full Adder 1 1 1 Full Adder handles carry in Three inputs: Cin, A, B
Two out: Cout, S 1 1 1

19 Full Adder Circuit Made from two half adders Add A & B
Add sum to carry

20 Full Adder Abstracted

21 Ripple Carry Adder Multibit adder : string of 1 bit full adders

22 Ripple Carry Adder Implemented with carry out & signed overflow:

23 Ripple Carry Adder Adding subtraction to adder Select line 0 : Normal
1 : Invert one pattern, add extra 1 via carry

24 Ripple Carry Adder Fun Fact
Carry signal needs to propagate from one adder to next 3 gates delay per bit

25 Carry Select Fun Fact Cary Select Adder
Calculate second block with both 0 and 1 carry Work in parallel with first Pick right answer when carry available

26 ALU ALU : Arithmetic Logic Unit In: Out: 2 Operands Control signal
Result based on select operation

27 ALU Harware to implement each desired op
Multiplexor to select desired one

28 1-Bit Simple ALU Processes two 1-bit inputs A, B
3 functions: AND (0), OR (1), Add (2) Selected with function select bits

29 1-Bit Simple ALU With selector to invert B input Can now also compute:
A OR ~B A AND ~B A + ~B

30 4-Bit Simple ALU Four 1-bit ALU's chained together

31 4-Bit Simple ALU AddOne allows for A + (~B) + 1 == A + (~B + 1) == A + (-B) == A - B


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